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| author | Peter Trommler <ptrommler@acm.org> | 2016-10-01 17:56:31 -0400 |
|---|---|---|
| committer | Ben Gamari <ben@smart-cactus.org> | 2016-10-01 20:01:29 -0400 |
| commit | ce3370e06165690e79a8eb22e5229b515157e00f (patch) | |
| tree | a9687d8dd7331816f3478ffef604ebf88d6b3101 /compiler/nativeGen/PPC | |
| parent | 1851349acd9e73f1c18d68f70d5cf7b46a843cb5 (diff) | |
| download | haskell-ce3370e06165690e79a8eb22e5229b515157e00f.tar.gz | |
PPC/CodeGen: fix lwa instruction generation
Opcode lwa is a 64-bit opcode and allows a DS-form only. This patch
generates lwa opcodes only when the offset is a multiple of 4.
Fixes #12621
Test Plan: validate
Reviewers: erikd, hvr, simonmar, austin, bgamari
Reviewed By: bgamari
Subscribers: thomie
Differential Revision: https://phabricator.haskell.org/D2547
GHC Trac Issues: #12621
Diffstat (limited to 'compiler/nativeGen/PPC')
| -rw-r--r-- | compiler/nativeGen/PPC/CodeGen.hs | 16 |
1 files changed, 12 insertions, 4 deletions
diff --git a/compiler/nativeGen/PPC/CodeGen.hs b/compiler/nativeGen/PPC/CodeGen.hs index d03a6e5c23..ead122b959 100644 --- a/compiler/nativeGen/PPC/CodeGen.hs +++ b/compiler/nativeGen/PPC/CodeGen.hs @@ -9,9 +9,8 @@ ----------------------------------------------------------------------------- -- This is a big module, but, if you pay attention to --- (a) the sectioning, (b) the type signatures, and --- (c) the #if blah_TARGET_ARCH} things, the --- structure should not be too overwhelming. +-- (a) the sectioning, and (b) the type signatures, +-- the structure should not be too overwhelming. module PPC.CodeGen ( cmmTopCodeGen, @@ -471,7 +470,8 @@ getRegister' _ (CmmMachOp (MO_UU_Conv W32 W64) [CmmLoad mem _]) = do return (Any II64 (\dst -> addr_code `snocOL` LD II32 dst addr)) getRegister' _ (CmmMachOp (MO_SS_Conv W32 W64) [CmmLoad mem _]) = do - Amode addr addr_code <- getAmode D mem + -- lwa is DS-form. See Note [Power instruction format] + Amode addr addr_code <- getAmode DS mem return (Any II64 (\dst -> addr_code `snocOL` LA II32 dst addr)) getRegister' dflags (CmmMachOp mop [x]) -- unary MachOps @@ -742,6 +742,14 @@ temporary, then do the other computation, and then use the temporary: ... (tmp) ... -} +{- Note [Power instruction format] +In some instructions the 16 bit offset must be a multiple of 4, i.e. +the two least significant bits mus be zero. The "Power ISA" specification +calls these instruction formats "DS-FORM" and the instructions with +arbitrary 16 bit offsets are "D-FORM". + +The Power ISA specification document can be obtained from www.power.org. +-} data InstrForm = D | DS getAmode :: InstrForm -> CmmExpr -> NatM Amode |