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| author | Abhiroop Sarkar <asiamgenius@gmail.com> | 2018-09-27 15:28:46 -0400 |
|---|---|---|
| committer | Marge Bot <ben+marge-bot@smart-cactus.org> | 2019-07-03 09:33:39 -0400 |
| commit | acd795583625401c5554f8e04ec7efca18814011 (patch) | |
| tree | 545e529eed21e78592ff326d4ebf9804095ad2cb /compiler/nativeGen/Reg.hs | |
| parent | df3e5b744db29c085f5bc05f8b609197bcbf9b0c (diff) | |
| download | haskell-acd795583625401c5554f8e04ec7efca18814011.tar.gz | |
Add support for SIMD operations in the NCG
This adds support for constructing vector types from Float#, Double# etc
and performing arithmetic operations on them
Cleaned-Up-By: Ben Gamari <ben@well-typed.com>
Diffstat (limited to 'compiler/nativeGen/Reg.hs')
| -rw-r--r-- | compiler/nativeGen/Reg.hs | 14 |
1 files changed, 11 insertions, 3 deletions
diff --git a/compiler/nativeGen/Reg.hs b/compiler/nativeGen/Reg.hs index 7f69ea01a4..dff2f07bf4 100644 --- a/compiler/nativeGen/Reg.hs +++ b/compiler/nativeGen/Reg.hs @@ -56,6 +56,7 @@ data VirtualReg | VirtualRegHi {-# UNPACK #-} !Unique -- High part of 2-word register | VirtualRegF {-# UNPACK #-} !Unique | VirtualRegD {-# UNPACK #-} !Unique + | VirtualRegVec {-# UNPACK #-} !Unique deriving (Eq, Show) @@ -69,6 +70,7 @@ instance Ord VirtualReg where compare (VirtualRegHi a) (VirtualRegHi b) = nonDetCmpUnique a b compare (VirtualRegF a) (VirtualRegF b) = nonDetCmpUnique a b compare (VirtualRegD a) (VirtualRegD b) = nonDetCmpUnique a b + compare (VirtualRegVec a) (VirtualRegVec b) = nonDetCmpUnique a b compare VirtualRegI{} _ = LT compare _ VirtualRegI{} = GT @@ -76,7 +78,8 @@ instance Ord VirtualReg where compare _ VirtualRegHi{} = GT compare VirtualRegF{} _ = LT compare _ VirtualRegF{} = GT - + compare VirtualRegVec{} _ = LT + compare _ VirtualRegVec{} = GT instance Uniquable VirtualReg where @@ -86,6 +89,7 @@ instance Uniquable VirtualReg where VirtualRegHi u -> u VirtualRegF u -> u VirtualRegD u -> u + VirtualRegVec u -> u instance Outputable VirtualReg where ppr reg @@ -95,8 +99,9 @@ instance Outputable VirtualReg where -- this code is kinda wrong on x86 -- because float and double occupy the same register set -- namely SSE2 register xmm0 .. xmm15 - VirtualRegF u -> text "%vFloat_" <> pprUniqueAlways u - VirtualRegD u -> text "%vDouble_" <> pprUniqueAlways u + VirtualRegF u -> text "%vFloat_" <> pprUniqueAlways u + VirtualRegD u -> text "%vDouble_" <> pprUniqueAlways u + VirtualRegVec u -> text "%vVec_" <> pprUniqueAlways u @@ -107,6 +112,7 @@ renameVirtualReg u r VirtualRegHi _ -> VirtualRegHi u VirtualRegF _ -> VirtualRegF u VirtualRegD _ -> VirtualRegD u + VirtualRegVec _ -> VirtualRegVec u classOfVirtualReg :: VirtualReg -> RegClass @@ -116,6 +122,8 @@ classOfVirtualReg vr VirtualRegHi{} -> RcInteger VirtualRegF{} -> RcFloat VirtualRegD{} -> RcDouble + -- Below is an awful, largely x86-specific hack + VirtualRegVec{} -> RcDouble |