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| author | Ben.Lippmeier@anu.edu.au <unknown> | 2009-02-04 03:41:07 +0000 |
|---|---|---|
| committer | Ben.Lippmeier@anu.edu.au <unknown> | 2009-02-04 03:41:07 +0000 |
| commit | a12e845684c10955bc594cdb20d1f13fae14873d (patch) | |
| tree | adaa06258fc5b1446281dc6ba45f3f841bf0d1f5 /compiler/nativeGen/RegAlloc/Linear | |
| parent | 9de520b7194c9d759147db98deb3cd8d47d0de76 (diff) | |
| download | haskell-a12e845684c10955bc594cdb20d1f13fae14873d.tar.gz | |
NCG: Rename MachRegs, MachInstrs -> Regs, Instrs to reflect arch specific naming
Diffstat (limited to 'compiler/nativeGen/RegAlloc/Linear')
| -rw-r--r-- | compiler/nativeGen/RegAlloc/Linear/Base.hs | 2 | ||||
| -rw-r--r-- | compiler/nativeGen/RegAlloc/Linear/JoinToTargets.hs | 4 | ||||
| -rw-r--r-- | compiler/nativeGen/RegAlloc/Linear/Main.hs | 4 | ||||
| -rw-r--r-- | compiler/nativeGen/RegAlloc/Linear/PPC/FreeRegs.hs | 2 | ||||
| -rw-r--r-- | compiler/nativeGen/RegAlloc/Linear/SPARC/FreeRegs.hs | 2 | ||||
| -rw-r--r-- | compiler/nativeGen/RegAlloc/Linear/State.hs | 4 | ||||
| -rw-r--r-- | compiler/nativeGen/RegAlloc/Linear/Stats.hs | 2 | ||||
| -rw-r--r-- | compiler/nativeGen/RegAlloc/Linear/X86/FreeRegs.hs | 2 |
8 files changed, 11 insertions, 11 deletions
diff --git a/compiler/nativeGen/RegAlloc/Linear/Base.hs b/compiler/nativeGen/RegAlloc/Linear/Base.hs index 3f9146cc02..ebd31076e3 100644 --- a/compiler/nativeGen/RegAlloc/Linear/Base.hs +++ b/compiler/nativeGen/RegAlloc/Linear/Base.hs @@ -22,7 +22,7 @@ import RegAlloc.Linear.FreeRegs import RegAlloc.Linear.StackMap import RegLiveness -import MachRegs +import Regs import Outputable import Unique diff --git a/compiler/nativeGen/RegAlloc/Linear/JoinToTargets.hs b/compiler/nativeGen/RegAlloc/Linear/JoinToTargets.hs index 1dd7da2f6e..5c6334685a 100644 --- a/compiler/nativeGen/RegAlloc/Linear/JoinToTargets.hs +++ b/compiler/nativeGen/RegAlloc/Linear/JoinToTargets.hs @@ -20,8 +20,8 @@ import RegAlloc.Linear.Base import RegAlloc.Linear.FreeRegs import BlockId -import MachInstrs -import MachRegs +import Instrs +import Regs import RegAllocInfo import RegLiveness import Cmm hiding (RegSet) diff --git a/compiler/nativeGen/RegAlloc/Linear/Main.hs b/compiler/nativeGen/RegAlloc/Linear/Main.hs index 3b1d5ca1e0..1d2c78b25f 100644 --- a/compiler/nativeGen/RegAlloc/Linear/Main.hs +++ b/compiler/nativeGen/RegAlloc/Linear/Main.hs @@ -98,8 +98,8 @@ import RegAlloc.Linear.Stats import RegAlloc.Linear.JoinToTargets import BlockId -import MachRegs -import MachInstrs +import Regs +import Instrs import RegAllocInfo import RegLiveness import Cmm hiding (RegSet) diff --git a/compiler/nativeGen/RegAlloc/Linear/PPC/FreeRegs.hs b/compiler/nativeGen/RegAlloc/Linear/PPC/FreeRegs.hs index 1e31625c37..6d8809df52 100644 --- a/compiler/nativeGen/RegAlloc/Linear/PPC/FreeRegs.hs +++ b/compiler/nativeGen/RegAlloc/Linear/PPC/FreeRegs.hs @@ -3,7 +3,7 @@ module RegAlloc.Linear.PPC.FreeRegs where -import MachRegs +import Regs import Outputable diff --git a/compiler/nativeGen/RegAlloc/Linear/SPARC/FreeRegs.hs b/compiler/nativeGen/RegAlloc/Linear/SPARC/FreeRegs.hs index e46d87dbf6..f8405327f7 100644 --- a/compiler/nativeGen/RegAlloc/Linear/SPARC/FreeRegs.hs +++ b/compiler/nativeGen/RegAlloc/Linear/SPARC/FreeRegs.hs @@ -3,7 +3,7 @@ module RegAlloc.Linear.SPARC.FreeRegs where -import MachRegs +import Regs import Outputable diff --git a/compiler/nativeGen/RegAlloc/Linear/State.hs b/compiler/nativeGen/RegAlloc/Linear/State.hs index 428b0caec9..a7f49d12d5 100644 --- a/compiler/nativeGen/RegAlloc/Linear/State.hs +++ b/compiler/nativeGen/RegAlloc/Linear/State.hs @@ -35,8 +35,8 @@ import RegAlloc.Linear.Base import RegAlloc.Linear.FreeRegs -import MachInstrs -import MachRegs +import Instrs +import Regs import RegAllocInfo import RegLiveness diff --git a/compiler/nativeGen/RegAlloc/Linear/Stats.hs b/compiler/nativeGen/RegAlloc/Linear/Stats.hs index f20ad60759..c139db731c 100644 --- a/compiler/nativeGen/RegAlloc/Linear/Stats.hs +++ b/compiler/nativeGen/RegAlloc/Linear/Stats.hs @@ -9,7 +9,7 @@ where import RegAlloc.Linear.Base import RegLiveness import RegAllocInfo -import MachInstrs +import Instrs import Cmm (GenBasicBlock(..)) import UniqFM diff --git a/compiler/nativeGen/RegAlloc/Linear/X86/FreeRegs.hs b/compiler/nativeGen/RegAlloc/Linear/X86/FreeRegs.hs index 5d7fc63854..1306deb159 100644 --- a/compiler/nativeGen/RegAlloc/Linear/X86/FreeRegs.hs +++ b/compiler/nativeGen/RegAlloc/Linear/X86/FreeRegs.hs @@ -3,7 +3,7 @@ module RegAlloc.Linear.X86.FreeRegs where -import MachRegs +import Regs import Data.Word import Data.Bits |