Merge remote-tracking branch 'origin/master' into newcg

* origin/master: (756 commits)
  don't crash if argv[0] == NULL (#7037)
  -package P was loading all versions of P in GHCi (#7030)
  Add a Note, copying text from #2437
  improve the --help docs a bit (#7008)
  Copy Data.HashTable's hashString into our Util module
  Build fix
  Build fixes
  Parse error: suggest brackets and indentation.
  Don't build the ghc DLL on Windows; works around trac #5987
  On Windows, detect if DLLs have too many symbols; trac #5987
  Add some more Integer rules; fixes #6111
  Fix PA dfun construction with silent superclass args
  Add silent superclass parameters to the vectoriser
  Add silent superclass parameters (again)
  Mention Generic1 in the user's guide
  Make the GHC API a little more powerful.
  tweak llvm version warning message
  New version of the patch for #5461.
  Fix Word64ToInteger conversion rule.
  Implemented feature request on reconfigurable pretty-printing in GHCi (#5461)
  ...

Conflicts:
	compiler/basicTypes/UniqSupply.lhs
	compiler/cmm/CmmBuildInfoTables.hs
	compiler/cmm/CmmLint.hs
	compiler/cmm/CmmOpt.hs
	compiler/cmm/CmmPipeline.hs
	compiler/cmm/CmmStackLayout.hs
	compiler/cmm/MkGraph.hs
	compiler/cmm/OldPprCmm.hs
	compiler/codeGen/CodeGen.lhs
	compiler/codeGen/StgCmm.hs
	compiler/codeGen/StgCmmBind.hs
	compiler/codeGen/StgCmmLayout.hs
	compiler/codeGen/StgCmmUtils.hs
	compiler/main/CodeOutput.lhs
	compiler/main/HscMain.hs
	compiler/nativeGen/AsmCodeGen.lhs
	compiler/simplStg/SimplStg.lhs

2 files changed, 29 insertions, 29 deletions

diff --git a/compiler/nativeGen/RegAlloc/Linear/FreeRegs.hs b/compiler/nativeGen/RegAlloc/Linear/FreeRegs.hs
index 6fbbd04fff..fd1fd272bd 100644
--- a/compiler/nativeGen/RegAlloc/Linear/FreeRegs.hs
+++ b/compiler/nativeGen/RegAlloc/Linear/FreeRegs.hs
@@ -68,11 +68,11 @@ instance FR SPARC.FreeRegs where
 maxSpillSlots :: Platform -> Int
 maxSpillSlots platform
               = case platformArch platform of
-                ArchX86     -> X86.Instr.maxSpillSlots True  -- 32bit
-                ArchX86_64  -> X86.Instr.maxSpillSlots False -- not 32bit
-                ArchPPC     -> PPC.Instr.maxSpillSlots
-                ArchSPARC   -> SPARC.Instr.maxSpillSlots
-                ArchARM _ _ -> panic "maxSpillSlots ArchARM"
-                ArchPPC_64  -> panic "maxSpillSlots ArchPPC_64"
-                ArchUnknown -> panic "maxSpillSlots ArchUnknown"
+                ArchX86       -> X86.Instr.maxSpillSlots True  -- 32bit
+                ArchX86_64    -> X86.Instr.maxSpillSlots False -- not 32bit
+                ArchPPC       -> PPC.Instr.maxSpillSlots
+                ArchSPARC     -> SPARC.Instr.maxSpillSlots
+                ArchARM _ _ _ -> panic "maxSpillSlots ArchARM"
+                ArchPPC_64    -> panic "maxSpillSlots ArchPPC_64"
+                ArchUnknown   -> panic "maxSpillSlots ArchUnknown"
 
diff --git a/compiler/nativeGen/RegAlloc/Linear/Main.hs b/compiler/nativeGen/RegAlloc/Linear/Main.hs
index fc0bde44a0..8c38fd1de6 100644
--- a/compiler/nativeGen/RegAlloc/Linear/Main.hs
+++ b/compiler/nativeGen/RegAlloc/Linear/Main.hs
@@ -127,7 +127,7 @@ import Control.Monad
 
 -- Allocate registers
 regAlloc
-        :: (PlatformOutputable instr, Instruction instr)
+        :: (Outputable instr, Instruction instr)
         => DynFlags
         -> LiveCmmDecl statics instr
         -> UniqSM (NatCmmDecl statics instr, Maybe RegAllocStats)
@@ -170,7 +170,7 @@ regAlloc _ (CmmProc _ _ _)
 --   an entry in the block map or it is the first block.
 --
 linearRegAlloc
-        :: (PlatformOutputable instr, Instruction instr)
+        :: (Outputable instr, Instruction instr)
         => DynFlags
         -> BlockId                      -- ^ the first block
         -> BlockMap RegSet              -- ^ live regs on entry to each basic block
@@ -180,16 +180,16 @@ linearRegAlloc
 linearRegAlloc dflags first_id block_live sccs
  = let platform = targetPlatform dflags
    in case platformArch platform of
-      ArchX86     -> linearRegAlloc' platform (frInitFreeRegs :: X86.FreeRegs)   first_id block_live sccs
-      ArchX86_64  -> linearRegAlloc' platform (frInitFreeRegs :: X86.FreeRegs)   first_id block_live sccs
-      ArchSPARC   -> linearRegAlloc' platform (frInitFreeRegs :: SPARC.FreeRegs) first_id block_live sccs
-      ArchPPC     -> linearRegAlloc' platform (frInitFreeRegs :: PPC.FreeRegs)   first_id block_live sccs
-      ArchARM _ _ -> panic "linearRegAlloc ArchARM"
-      ArchPPC_64  -> panic "linearRegAlloc ArchPPC_64"
-      ArchUnknown -> panic "linearRegAlloc ArchUnknown"
+      ArchX86       -> linearRegAlloc' platform (frInitFreeRegs :: X86.FreeRegs)   first_id block_live sccs
+      ArchX86_64    -> linearRegAlloc' platform (frInitFreeRegs :: X86.FreeRegs)   first_id block_live sccs
+      ArchSPARC     -> linearRegAlloc' platform (frInitFreeRegs :: SPARC.FreeRegs) first_id block_live sccs
+      ArchPPC       -> linearRegAlloc' platform (frInitFreeRegs :: PPC.FreeRegs)   first_id block_live sccs
+      ArchARM _ _ _ -> panic "linearRegAlloc ArchARM"
+      ArchPPC_64    -> panic "linearRegAlloc ArchPPC_64"
+      ArchUnknown   -> panic "linearRegAlloc ArchUnknown"
 
 linearRegAlloc'
-        :: (FR freeRegs, PlatformOutputable instr, Instruction instr)
+        :: (FR freeRegs, Outputable instr, Instruction instr)
         => Platform
         -> freeRegs
         -> BlockId                      -- ^ the first block
@@ -205,7 +205,7 @@ linearRegAlloc' platform initFreeRegs first_id block_live sccs
         return  (blocks, stats)
 
 
-linearRA_SCCs :: (FR freeRegs, Instruction instr, PlatformOutputable instr)
+linearRA_SCCs :: (FR freeRegs, Instruction instr, Outputable instr)
               => Platform
               -> BlockId
               -> BlockMap RegSet
@@ -241,7 +241,7 @@ linearRA_SCCs platform first_id block_live blocksAcc (CyclicSCC blocks : sccs)
    more sanity checking to guard against this eventuality.
 -}
 
-process :: (FR freeRegs, Instruction instr, PlatformOutputable instr)
+process :: (FR freeRegs, Instruction instr, Outputable instr)
         => Platform
         -> BlockId
         -> BlockMap RegSet
@@ -286,7 +286,7 @@ process platform first_id block_live (b@(BasicBlock id _) : blocks)
 -- | Do register allocation on this basic block
 --
 processBlock
-        :: (FR freeRegs, PlatformOutputable instr, Instruction instr)
+        :: (FR freeRegs, Outputable instr, Instruction instr)
         => Platform
         -> BlockMap RegSet              -- ^ live regs on entry to each basic block
         -> LiveBasicBlock instr         -- ^ block to do register allocation on
@@ -321,7 +321,7 @@ initBlock id
 
 -- | Do allocation for a sequence of instructions.
 linearRA
-        :: (FR freeRegs, PlatformOutputable instr, Instruction instr)
+        :: (FR freeRegs, Outputable instr, Instruction instr)
         => Platform
         -> BlockMap RegSet                      -- ^ map of what vregs are live on entry to each block.
         -> [instr]                              -- ^ accumulator for instructions already processed.
@@ -350,7 +350,7 @@ linearRA platform block_live accInstr accFixups id (instr:instrs)
 
 -- | Do allocation for a single instruction.
 raInsn
-        :: (FR freeRegs, PlatformOutputable instr, Instruction instr)
+        :: (FR freeRegs, Outputable instr, Instruction instr)
         => Platform
         -> BlockMap RegSet                      -- ^ map of what vregs are love on entry to each block.
         -> [instr]                              -- ^ accumulator for instructions already processed.
@@ -410,11 +410,11 @@ raInsn platform block_live new_instrs id (LiveInstr (Instr instr) (Just live))
                         (uniqSetToList $ liveDieWrite live)
 
 
-raInsn platform _ _ _ instr
-        = pprPanic "raInsn" (text "no match for:" <> pprPlatform platform instr)
+raInsn _ _ _ _ instr
+        = pprPanic "raInsn" (text "no match for:" <> ppr instr)
 
 
-genRaInsn :: (FR freeRegs, Instruction instr, PlatformOutputable instr)
+genRaInsn :: (FR freeRegs, Instruction instr, Outputable instr)
           => Platform
           -> BlockMap RegSet
           -> [instr]
@@ -554,7 +554,7 @@ releaseRegs regs = do
 
 
 saveClobberedTemps
-        :: (PlatformOutputable instr, Instruction instr)
+        :: (Outputable instr, Instruction instr)
         => Platform
         -> [RealReg]            -- real registers clobbered by this instruction
         -> [Reg]                -- registers which are no longer live after this insn
@@ -647,7 +647,7 @@ data SpillLoc = ReadMem StackSlot  -- reading from register only in memory
 --   the list of free registers and free stack slots.
 
 allocateRegsAndSpill
-        :: (FR freeRegs, PlatformOutputable instr, Instruction instr)
+        :: (FR freeRegs, Outputable instr, Instruction instr)
         => Platform
         -> Bool                 -- True <=> reading (load up spilled regs)
         -> [VirtualReg]         -- don't push these out
@@ -692,7 +692,7 @@ allocateRegsAndSpill platform reading keep spills alloc (r:rs)
 
 -- reading is redundant with reason, but we keep it around because it's
 -- convenient and it maintains the recursive structure of the allocator. -- EZY
-allocRegsAndSpill_spill :: (FR freeRegs, Instruction instr, PlatformOutputable instr)
+allocRegsAndSpill_spill :: (FR freeRegs, Instruction instr, Outputable instr)
                         => Platform
                         -> Bool
                         -> [VirtualReg]
@@ -798,7 +798,7 @@ newLocation _ my_reg = InReg my_reg
 
 -- | Load up a spilled temporary if we need to (read from memory).
 loadTemp
-        :: (PlatformOutputable instr, Instruction instr)
+        :: (Outputable instr, Instruction instr)
         => Platform
         -> VirtualReg   -- the temp being loaded
         -> SpillLoc     -- the current location of this temp