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| author | Ian Lynagh <ian@well-typed.com> | 2012-08-21 19:50:32 +0100 |
|---|---|---|
| committer | Ian Lynagh <ian@well-typed.com> | 2012-08-21 19:50:32 +0100 |
| commit | b6b6311b1c8894fe9e157c5215decf4674d48cad (patch) | |
| tree | f907de4920f54c23bab47e86a07c06c2491f5a9e /compiler/nativeGen/RegAlloc | |
| parent | ac21fdb440d4cf44134f609d2aec73e1fcacf424 (diff) | |
| download | haskell-b6b6311b1c8894fe9e157c5215decf4674d48cad.tar.gz | |
Pass platform down to lastint
Diffstat (limited to 'compiler/nativeGen/RegAlloc')
| -rw-r--r-- | compiler/nativeGen/RegAlloc/Linear/FreeRegs.hs | 6 | ||||
| -rw-r--r-- | compiler/nativeGen/RegAlloc/Linear/Main.hs | 4 | ||||
| -rw-r--r-- | compiler/nativeGen/RegAlloc/Linear/X86/FreeRegs.hs | 6 |
3 files changed, 8 insertions, 8 deletions
diff --git a/compiler/nativeGen/RegAlloc/Linear/FreeRegs.hs b/compiler/nativeGen/RegAlloc/Linear/FreeRegs.hs index 5fc389b89e..724d7d6b25 100644 --- a/compiler/nativeGen/RegAlloc/Linear/FreeRegs.hs +++ b/compiler/nativeGen/RegAlloc/Linear/FreeRegs.hs @@ -43,7 +43,7 @@ import qualified X86.Instr class Show freeRegs => FR freeRegs where frAllocateReg :: RealReg -> freeRegs -> freeRegs - frGetFreeRegs :: RegClass -> freeRegs -> [RealReg] + frGetFreeRegs :: Platform -> RegClass -> freeRegs -> [RealReg] frInitFreeRegs :: Platform -> freeRegs frReleaseReg :: RealReg -> freeRegs -> freeRegs @@ -55,13 +55,13 @@ instance FR X86.FreeRegs where instance FR PPC.FreeRegs where frAllocateReg = PPC.allocateReg - frGetFreeRegs = PPC.getFreeRegs + frGetFreeRegs = \_ -> PPC.getFreeRegs frInitFreeRegs = \_ -> PPC.initFreeRegs frReleaseReg = PPC.releaseReg instance FR SPARC.FreeRegs where frAllocateReg = SPARC.allocateReg - frGetFreeRegs = SPARC.getFreeRegs + frGetFreeRegs = \_ -> SPARC.getFreeRegs frInitFreeRegs = \_ -> SPARC.initFreeRegs frReleaseReg = SPARC.releaseReg diff --git a/compiler/nativeGen/RegAlloc/Linear/Main.hs b/compiler/nativeGen/RegAlloc/Linear/Main.hs index 7d6e85e664..54c6990948 100644 --- a/compiler/nativeGen/RegAlloc/Linear/Main.hs +++ b/compiler/nativeGen/RegAlloc/Linear/Main.hs @@ -604,7 +604,7 @@ saveClobberedTemps platform clobbered dying = do freeRegs <- getFreeRegsR let regclass = targetClassOfRealReg platform reg - freeRegs_thisClass = frGetFreeRegs regclass freeRegs + freeRegs_thisClass = frGetFreeRegs platform regclass freeRegs case filter (`notElem` clobbered) freeRegs_thisClass of @@ -745,7 +745,7 @@ allocRegsAndSpill_spill :: (FR freeRegs, Instruction instr, Outputable instr) allocRegsAndSpill_spill platform reading keep spills alloc r rs assig spill_loc = do freeRegs <- getFreeRegsR - let freeRegs_thisClass = frGetFreeRegs (classOfVirtualReg r) freeRegs + let freeRegs_thisClass = frGetFreeRegs platform (classOfVirtualReg r) freeRegs case freeRegs_thisClass of diff --git a/compiler/nativeGen/RegAlloc/Linear/X86/FreeRegs.hs b/compiler/nativeGen/RegAlloc/Linear/X86/FreeRegs.hs index debdf3cd03..03c27f45e2 100644 --- a/compiler/nativeGen/RegAlloc/Linear/X86/FreeRegs.hs +++ b/compiler/nativeGen/RegAlloc/Linear/X86/FreeRegs.hs @@ -40,12 +40,12 @@ initFreeRegs :: Platform -> FreeRegs initFreeRegs platform = foldr releaseReg noFreeRegs (allocatableRegs platform) -getFreeRegs :: RegClass -> FreeRegs -> [RealReg] -- lazilly -getFreeRegs cls f = go f 0 +getFreeRegs :: Platform -> RegClass -> FreeRegs -> [RealReg] -- lazilly +getFreeRegs platform cls f = go f 0 where go 0 _ = [] go n m - | n .&. 1 /= 0 && classOfRealReg (RealRegSingle m) == cls + | n .&. 1 /= 0 && classOfRealReg platform (RealRegSingle m) == cls = RealRegSingle m : (go (n `shiftR` 1) $! (m+1)) | otherwise |