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| author | Karel Gardas <karel.gardas@centrum.cz> | 2011-08-20 23:49:48 +0200 |
|---|---|---|
| committer | Karel Gardas <karel.gardas@centrum.cz> | 2011-08-21 08:50:57 +0200 |
| commit | bab9a72d7f12a88bb38677db03ed4c956d0a7d99 (patch) | |
| tree | c0a703e2770e7cf062904641f79cda08f6c9ca2d /compiler/nativeGen/RegAlloc | |
| parent | 2906db6c3a3f1000bd7347c7d8e45e65eb2806cb (diff) | |
| download | haskell-bab9a72d7f12a88bb38677db03ed4c956d0a7d99.tar.gz | |
enhance ArchARM with ISA and ISA extensions
This patch enhances ArchARM with ARM ISA and ISA extensions details
as is suggested in the comment in Platform.hs file. The patch is needed
by future patch which will use ARM ISA information in order to pass
appropriate command-line option to the LLVM llc tool.
Diffstat (limited to 'compiler/nativeGen/RegAlloc')
| -rw-r--r-- | compiler/nativeGen/RegAlloc/Graph/TrivColorable.hs | 8 | ||||
| -rw-r--r-- | compiler/nativeGen/RegAlloc/Linear/FreeRegs.hs | 2 | ||||
| -rw-r--r-- | compiler/nativeGen/RegAlloc/Linear/Main.hs | 2 |
3 files changed, 6 insertions, 6 deletions
diff --git a/compiler/nativeGen/RegAlloc/Graph/TrivColorable.hs b/compiler/nativeGen/RegAlloc/Graph/TrivColorable.hs index e62b4a9abb..6067f23ade 100644 --- a/compiler/nativeGen/RegAlloc/Graph/TrivColorable.hs +++ b/compiler/nativeGen/RegAlloc/Graph/TrivColorable.hs @@ -112,7 +112,7 @@ trivColorable platform virtualRegSqueeze realRegSqueeze RcInteger conflicts excl ArchPPC -> 16 ArchSPARC -> 14 ArchPPC_64 -> panic "trivColorable ArchPPC_64" - ArchARM -> panic "trivColorable ArchARM" + ArchARM _ _ -> panic "trivColorable ArchARM" ArchUnknown -> panic "trivColorable ArchUnknown") , count2 <- accSqueeze (_ILIT(0)) cALLOCATABLE_REGS_INTEGER (virtualRegSqueeze RcInteger) @@ -132,7 +132,7 @@ trivColorable platform virtualRegSqueeze realRegSqueeze RcFloat conflicts exclus ArchPPC -> 0 ArchSPARC -> 22 ArchPPC_64 -> panic "trivColorable ArchPPC_64" - ArchARM -> panic "trivColorable ArchARM" + ArchARM _ _ -> panic "trivColorable ArchARM" ArchUnknown -> panic "trivColorable ArchUnknown") , count2 <- accSqueeze (_ILIT(0)) cALLOCATABLE_REGS_FLOAT (virtualRegSqueeze RcFloat) @@ -152,7 +152,7 @@ trivColorable platform virtualRegSqueeze realRegSqueeze RcDouble conflicts exclu ArchPPC -> 26 ArchSPARC -> 11 ArchPPC_64 -> panic "trivColorable ArchPPC_64" - ArchARM -> panic "trivColorable ArchARM" + ArchARM _ _ -> panic "trivColorable ArchARM" ArchUnknown -> panic "trivColorable ArchUnknown") , count2 <- accSqueeze (_ILIT(0)) cALLOCATABLE_REGS_DOUBLE (virtualRegSqueeze RcDouble) @@ -172,7 +172,7 @@ trivColorable platform virtualRegSqueeze realRegSqueeze RcDoubleSSE conflicts ex ArchPPC -> 0 ArchSPARC -> 0 ArchPPC_64 -> panic "trivColorable ArchPPC_64" - ArchARM -> panic "trivColorable ArchARM" + ArchARM _ _ -> panic "trivColorable ArchARM" ArchUnknown -> panic "trivColorable ArchUnknown") , count2 <- accSqueeze (_ILIT(0)) cALLOCATABLE_REGS_SSE (virtualRegSqueeze RcDoubleSSE) diff --git a/compiler/nativeGen/RegAlloc/Linear/FreeRegs.hs b/compiler/nativeGen/RegAlloc/Linear/FreeRegs.hs index 5a413d341e..809e185d9b 100644 --- a/compiler/nativeGen/RegAlloc/Linear/FreeRegs.hs +++ b/compiler/nativeGen/RegAlloc/Linear/FreeRegs.hs @@ -65,7 +65,7 @@ maxSpillSlots platform ArchX86_64 -> X86.Instr.maxSpillSlots ArchPPC -> PPC.Instr.maxSpillSlots ArchSPARC -> SPARC.Instr.maxSpillSlots - ArchARM -> panic "maxSpillSlots ArchARM" + ArchARM _ _ -> panic "maxSpillSlots ArchARM" ArchPPC_64 -> panic "maxSpillSlots ArchPPC_64" ArchUnknown -> panic "maxSpillSlots ArchUnknown" diff --git a/compiler/nativeGen/RegAlloc/Linear/Main.hs b/compiler/nativeGen/RegAlloc/Linear/Main.hs index 8fa758d063..f1af6a5e39 100644 --- a/compiler/nativeGen/RegAlloc/Linear/Main.hs +++ b/compiler/nativeGen/RegAlloc/Linear/Main.hs @@ -184,7 +184,7 @@ linearRegAlloc dflags first_id block_live sccs ArchX86_64 -> linearRegAlloc' platform (frInitFreeRegs :: X86.FreeRegs) first_id block_live sccs ArchSPARC -> linearRegAlloc' platform (frInitFreeRegs :: SPARC.FreeRegs) first_id block_live sccs ArchPPC -> linearRegAlloc' platform (frInitFreeRegs :: PPC.FreeRegs) first_id block_live sccs - ArchARM -> panic "linearRegAlloc ArchARM" + ArchARM _ _ -> panic "linearRegAlloc ArchARM" ArchPPC_64 -> panic "linearRegAlloc ArchPPC_64" ArchUnknown -> panic "linearRegAlloc ArchUnknown" |