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authorBen.Lippmeier@anu.edu.au <unknown>2007-08-23 13:26:14 +0000
committerBen.Lippmeier@anu.edu.au <unknown>2007-08-23 13:26:14 +0000
commit9e5cd691a00f5e53bdd735df4d5a33b72eeafedf (patch)
tree7c0e429b446cbf62d2622ab281f31ca2b67af8a4 /compiler/nativeGen/RegAllocLinear.hs
parent77b99dc38036e2908101984c8394ac16f6daa4e0 (diff)
downloadhaskell-9e5cd691a00f5e53bdd735df4d5a33b72eeafedf.tar.gz
Eliminate more dead reg->reg moves in linear allocator
Diffstat (limited to 'compiler/nativeGen/RegAllocLinear.hs')
-rw-r--r--compiler/nativeGen/RegAllocLinear.hs10
1 files changed, 9 insertions, 1 deletions
diff --git a/compiler/nativeGen/RegAllocLinear.hs b/compiler/nativeGen/RegAllocLinear.hs
index d9ff1214bc..d761bae3c0 100644
--- a/compiler/nativeGen/RegAllocLinear.hs
+++ b/compiler/nativeGen/RegAllocLinear.hs
@@ -498,7 +498,15 @@ genRaInsn block_live new_instrs instr r_dying w_dying =
-- (j) free up stack slots for dead spilled regs
-- TODO (can't be bothered right now)
- return (patched_instr : w_spills ++ reverse r_spills
+ -- erase reg->reg moves where the source and destination are the same.
+ -- If the src temp didn't die in this instr but happened to be allocated
+ -- to the same real reg as the destination, then we can erase the move anyway.
+ squashed_instr = case isRegRegMove patched_instr of
+ Just (src, dst)
+ | src == dst -> []
+ _ -> [patched_instr]
+
+ return (squashed_instr ++ w_spills ++ reverse r_spills
++ clobber_saves ++ new_instrs,
fixup_blocks)
}}