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| author | Ben Gamari <ben@smart-cactus.org> | 2019-07-09 14:49:32 -0400 |
|---|---|---|
| committer | Marge Bot <ben+marge-bot@smart-cactus.org> | 2019-07-16 02:40:43 -0400 |
| commit | db948daea6c01c073f8d09a79fa5adda279fbf0c (patch) | |
| tree | 50fdb60bdd06a12dab101bf4fca3358fec0ad43d /compiler/nativeGen/SPARC/Regs.hs | |
| parent | 5728d9faafe410d1e0c3a070bb8882721470b798 (diff) | |
| download | haskell-db948daea6c01c073f8d09a79fa5adda279fbf0c.tar.gz | |
Revert "Add support for SIMD operations in the NCG"
Unfortunately this will require more work; register allocation is
quite broken.
This reverts commit acd795583625401c5554f8e04ec7efca18814011.
Diffstat (limited to 'compiler/nativeGen/SPARC/Regs.hs')
| -rw-r--r-- | compiler/nativeGen/SPARC/Regs.hs | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/compiler/nativeGen/SPARC/Regs.hs b/compiler/nativeGen/SPARC/Regs.hs index e46dbd0d38..0d7edc346a 100644 --- a/compiler/nativeGen/SPARC/Regs.hs +++ b/compiler/nativeGen/SPARC/Regs.hs @@ -104,6 +104,7 @@ virtualRegSqueeze cls vr VirtualRegD{} -> 1 _other -> 0 + {-# INLINE realRegSqueeze #-} realRegSqueeze :: RegClass -> RealReg -> Int @@ -133,6 +134,7 @@ realRegSqueeze cls rr RealRegPair{} -> 1 + -- | All the allocatable registers in the machine, -- including register pairs. allRealRegs :: [RealReg] |