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authorAustin Seipp <austin@well-typed.com>2014-07-18 22:25:29 -0500
committerAustin Seipp <austin@well-typed.com>2014-07-20 16:55:49 -0500
commitc7545999cbf585d905d1a0e519b90ef13cbc8c54 (patch)
tree312f475cb1dc2accd9bbd4b1a2a1067589d1a96a /compiler/nativeGen
parente193380c49a2a5a25efcadbf4afb7bfb48c7034c (diff)
downloadhaskell-c7545999cbf585d905d1a0e519b90ef13cbc8c54.tar.gz
nativeGen: detabify/dewhitespace TargetReg
Signed-off-by: Austin Seipp <austin@well-typed.com>
Diffstat (limited to 'compiler/nativeGen')
-rw-r--r--compiler/nativeGen/TargetReg.hs34
1 files changed, 12 insertions, 22 deletions
diff --git a/compiler/nativeGen/TargetReg.hs b/compiler/nativeGen/TargetReg.hs
index daf1e254c8..96c1777795 100644
--- a/compiler/nativeGen/TargetReg.hs
+++ b/compiler/nativeGen/TargetReg.hs
@@ -1,28 +1,20 @@
{-# LANGUAGE CPP #-}
-{-# OPTIONS_GHC -fno-warn-tabs #-}
--- The above warning supression flag is a temporary kludge.
--- While working on this module you are encouraged to remove it and
--- detab the module (please do the detabbing in a separate patch). See
--- http://ghc.haskell.org/trac/ghc/wiki/Commentary/CodingStyle#TabsvsSpaces
--- for details
-
-- | Hard wired things related to registers.
--- This is module is preventing the native code generator being able to
--- emit code for non-host architectures.
+-- This is module is preventing the native code generator being able to
+-- emit code for non-host architectures.
--
--- TODO: Do a better job of the overloading, and eliminate this module.
--- We'd probably do better with a Register type class, and hook this to
--- Instruction somehow.
+-- TODO: Do a better job of the overloading, and eliminate this module.
+-- We'd probably do better with a Register type class, and hook this to
+-- Instruction somehow.
--
--- TODO: We should also make arch specific versions of RegAlloc.Graph.TrivColorable
-
+-- TODO: We should also make arch specific versions of RegAlloc.Graph.TrivColorable
module TargetReg (
- targetVirtualRegSqueeze,
- targetRealRegSqueeze,
- targetClassOfRealReg,
- targetMkVirtualReg,
- targetRegDotColor,
- targetClassOfReg
+ targetVirtualRegSqueeze,
+ targetRealRegSqueeze,
+ targetClassOfRealReg,
+ targetMkVirtualReg,
+ targetRegDotColor,
+ targetClassOfReg
)
where
@@ -132,5 +124,3 @@ targetClassOfReg platform reg
= case reg of
RegVirtual vr -> classOfVirtualReg vr
RegReal rr -> targetClassOfRealReg platform rr
-
-