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authorGabor Greif <ggreif@gmail.com>2014-02-01 21:26:23 +0100
committerGabor Greif <ggreif@gmail.com>2014-02-01 21:26:23 +0100
commitd5fb6709df641010fb50bd120abd10257f4691b7 (patch)
tree06ee272eeb8df13ab0c058558bcebe9359da8461 /compiler/nativeGen
parent78afa2078e474c9e8fd3d0f347c5652f296d5248 (diff)
downloadhaskell-d5fb6709df641010fb50bd120abd10257f4691b7.tar.gz
Fix a popular typo in comments
Diffstat (limited to 'compiler/nativeGen')
-rw-r--r--compiler/nativeGen/RegAlloc/Graph/TrivColorable.hs2
-rw-r--r--compiler/nativeGen/SPARC/CodeGen/Gen32.hs2
2 files changed, 2 insertions, 2 deletions
diff --git a/compiler/nativeGen/RegAlloc/Graph/TrivColorable.hs b/compiler/nativeGen/RegAlloc/Graph/TrivColorable.hs
index df3c7d6d41..b5006ecfba 100644
--- a/compiler/nativeGen/RegAlloc/Graph/TrivColorable.hs
+++ b/compiler/nativeGen/RegAlloc/Graph/TrivColorable.hs
@@ -30,7 +30,7 @@ import Panic
-- (which are disjoint) ie. x86, x86_64 and ppc
--
-- The number of allocatable regs is hard coded in here so we can do
--- a fast comparision in trivColorable.
+-- a fast comparison in trivColorable.
--
-- It's ok if these numbers are _less_ than the actual number of free
-- regs, but they can't be more or the register conflict
diff --git a/compiler/nativeGen/SPARC/CodeGen/Gen32.hs b/compiler/nativeGen/SPARC/CodeGen/Gen32.hs
index 43b792a840..df876b4622 100644
--- a/compiler/nativeGen/SPARC/CodeGen/Gen32.hs
+++ b/compiler/nativeGen/SPARC/CodeGen/Gen32.hs
@@ -606,7 +606,7 @@ coerceFlt2Dbl x = do
-- Condition Codes -------------------------------------------------------------
--
--- Evaluate a comparision, and get the result into a register.
+-- Evaluate a comparison, and get the result into a register.
--
-- Do not fill the delay slots here. you will confuse the register allocator.
--