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| author | Peter Trommler <ptrommler@acm.org> | 2019-02-24 17:11:00 +0100 |
|---|---|---|
| committer | Marge Bot <ben+marge-bot@smart-cactus.org> | 2019-02-27 09:59:59 -0500 |
| commit | 5c084e0468be46f5ab48b2c1669a7e4d4d0f3c43 (patch) | |
| tree | 148d5b9dcae8f5f3701bc05a0a0d89386a33a1d7 /docs | |
| parent | 5bc195b1fe788e9a900a15fbe473967850517c3e (diff) | |
| download | haskell-5c084e0468be46f5ab48b2c1669a7e4d4d0f3c43.tar.gz | |
RTS: Add missing memory barrier
In the work stealing queue a load-load-barrier is required to ensure
that a read of queue data cannot be reordered before a read of the
bottom pointer into the queue.
The added load-load-barrier ensures that the ordering of writes enforced
at the end of `pushWSDeque` is also respected in the order of reads in
`stealWSDeque_`. In other words, when reading `q->bottom` we want to make
sure that we see the updates to `q->elements`.
Fixes #13633
Diffstat (limited to 'docs')
0 files changed, 0 insertions, 0 deletions