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| author | Andreas Schwab <schwab@suse.de> | 2020-10-02 23:49:01 +0200 |
|---|---|---|
| committer | Marge Bot <ben+marge-bot@smart-cactus.org> | 2021-03-05 14:01:56 -0500 |
| commit | 31e265c1df948d1bcc82d08affe995fd1d1c1438 (patch) | |
| tree | 4a7cc73979d7276946b7435307359d5a4481d574 /includes/stg/SMP.h | |
| parent | 6141aef49b37297e94c9e33a977438c2de15d086 (diff) | |
| download | haskell-31e265c1df948d1bcc82d08affe995fd1d1c1438.tar.gz | |
Implement riscv64 LLVM backend
This enables a registerised build for the riscv64 architecture.
Diffstat (limited to 'includes/stg/SMP.h')
| -rw-r--r-- | includes/stg/SMP.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/includes/stg/SMP.h b/includes/stg/SMP.h index 589bde8266..57eb618592 100644 --- a/includes/stg/SMP.h +++ b/includes/stg/SMP.h @@ -395,6 +395,8 @@ write_barrier(void) { __asm__ __volatile__ ("" : : : "memory"); #elif defined(arm_HOST_ARCH) || defined(aarch64_HOST_ARCH) __asm__ __volatile__ ("dmb st" : : : "memory"); +#elif defined(riscv64_HOST_ARCH) + __asm__ __volatile__ ("fence w,w" : : : "memory"); #else #error memory barriers unimplemented on this architecture #endif @@ -419,6 +421,8 @@ store_load_barrier(void) { __asm__ __volatile__ ("dmb" : : : "memory"); #elif defined(aarch64_HOST_ARCH) __asm__ __volatile__ ("dmb sy" : : : "memory"); +#elif defined(riscv64_HOST_ARCH) + __asm__ __volatile__ ("fence w,r" : : : "memory"); #else #error memory barriers unimplemented on this architecture #endif @@ -444,6 +448,8 @@ load_load_barrier(void) { __asm__ __volatile__ ("dmb" : : : "memory"); #elif defined(aarch64_HOST_ARCH) __asm__ __volatile__ ("dmb sy" : : : "memory"); +#elif defined(riscv64_HOST_ARCH) + __asm__ __volatile__ ("fence w,r" : : : "memory"); #else #error memory barriers unimplemented on this architecture #endif |