diff options
| author | Andreas Schwab <schwab@suse.de> | 2020-10-02 23:49:01 +0200 |
|---|---|---|
| committer | Matthew Pickering <matthewtpickering@gmail.com> | 2021-03-05 07:52:43 +0000 |
| commit | c5fb25493eebaed633b78926ba085c4819a1d191 (patch) | |
| tree | d9cded0284c5a8de6b1c8c30c55feb89344c9cd8 /includes/stg/SMP.h | |
| parent | 6467a48e64ce5ccea29099cb89962e879cded91c (diff) | |
| download | haskell-wip/riscv-backend.tar.gz | |
Implement riscv64 LLVM backendwip/riscv-backend
This enables a registerised build for the riscv64 architecture.
Diffstat (limited to 'includes/stg/SMP.h')
| -rw-r--r-- | includes/stg/SMP.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/includes/stg/SMP.h b/includes/stg/SMP.h index 589bde8266..57eb618592 100644 --- a/includes/stg/SMP.h +++ b/includes/stg/SMP.h @@ -395,6 +395,8 @@ write_barrier(void) { __asm__ __volatile__ ("" : : : "memory"); #elif defined(arm_HOST_ARCH) || defined(aarch64_HOST_ARCH) __asm__ __volatile__ ("dmb st" : : : "memory"); +#elif defined(riscv64_HOST_ARCH) + __asm__ __volatile__ ("fence w,w" : : : "memory"); #else #error memory barriers unimplemented on this architecture #endif @@ -419,6 +421,8 @@ store_load_barrier(void) { __asm__ __volatile__ ("dmb" : : : "memory"); #elif defined(aarch64_HOST_ARCH) __asm__ __volatile__ ("dmb sy" : : : "memory"); +#elif defined(riscv64_HOST_ARCH) + __asm__ __volatile__ ("fence w,r" : : : "memory"); #else #error memory barriers unimplemented on this architecture #endif @@ -444,6 +448,8 @@ load_load_barrier(void) { __asm__ __volatile__ ("dmb" : : : "memory"); #elif defined(aarch64_HOST_ARCH) __asm__ __volatile__ ("dmb sy" : : : "memory"); +#elif defined(riscv64_HOST_ARCH) + __asm__ __volatile__ ("fence w,r" : : : "memory"); #else #error memory barriers unimplemented on this architecture #endif |