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| author | Ben Gamari <bgamari.foss@gmail.com> | 2016-01-25 21:19:04 +0100 |
|---|---|---|
| committer | Ben Gamari <ben@smart-cactus.org> | 2016-01-25 21:19:05 +0100 |
| commit | 9fe7d20e2e5c60325ce04f476bc89fae06e43208 (patch) | |
| tree | 8b9e1efbe53fbbee8ff8c4c20459d8fd5f859a18 /includes/stg | |
| parent | f0f63b39783055b2c0c1a8db8c22749afa6d7329 (diff) | |
| download | haskell-9fe7d20e2e5c60325ce04f476bc89fae06e43208.tar.gz | |
Ensure that we don't produce code for pre-ARMv7 without barriers
We are unable to produce load/store barriers for pre-ARMv7 targets.
Phab:D894 added dummy cases to SMP.h for these barriers to prevent the
build from failing under the assumption that there are no SMP-capable
devices of this vintage. However, #10433 points out that it is more
correct to simply set NOSMP for such targets.
Tested By: rwbarton
Test Plan: Validate
Reviewers: erikd, rwbarton, austin
Reviewed By: rwbarton
Subscribers: thomie
Differential Revision: https://phabricator.haskell.org/D1704
GHC Trac Issues: #10433
Diffstat (limited to 'includes/stg')
| -rw-r--r-- | includes/stg/SMP.h | 17 |
1 files changed, 3 insertions, 14 deletions
diff --git a/includes/stg/SMP.h b/includes/stg/SMP.h index b0636d5b65..756f0401ab 100644 --- a/includes/stg/SMP.h +++ b/includes/stg/SMP.h @@ -372,9 +372,7 @@ write_barrier(void) { #elif sparc_HOST_ARCH /* Sparc in TSO mode does not require store/store barriers. */ __asm__ __volatile__ ("" : : : "memory"); -#elif arm_HOST_ARCH && defined(arm_HOST_ARCH_PRE_ARMv7) - __asm__ __volatile__ ("" : : : "memory"); -#elif (arm_HOST_ARCH && !defined(arm_HOST_ARCH_PRE_ARMv7)) || aarch64_HOST_ARCH +#elif (arm_HOST_ARCH) || aarch64_HOST_ARCH __asm__ __volatile__ ("dmb st" : : : "memory"); #else #error memory barriers unimplemented on this architecture @@ -393,14 +391,7 @@ store_load_barrier(void) { __asm__ __volatile__ ("sync" : : : "memory"); #elif sparc_HOST_ARCH __asm__ __volatile__ ("membar #StoreLoad" : : : "memory"); -#elif arm_HOST_ARCH && defined(arm_HOST_ARCH_PRE_ARMv7) - // TODO FIXME: This case probably isn't totally correct - just because we - // use a pre-ARMv7 toolchain (e.g. to target an old Android device), doesn't - // mean the binary won't run on a newer ARMv7 system - in which case it - // needs a proper barrier. So we should rethink this - // - Reid - __asm__ __volatile__ ("" : : : "memory"); -#elif arm_HOST_ARCH && !defined(arm_HOST_ARCH_PRE_ARMv7) +#elif arm_HOST_ARCH __asm__ __volatile__ ("dmb" : : : "memory"); #elif aarch64_HOST_ARCH __asm__ __volatile__ ("dmb sy" : : : "memory"); @@ -422,9 +413,7 @@ load_load_barrier(void) { #elif sparc_HOST_ARCH /* Sparc in TSO mode does not require load/load barriers. */ __asm__ __volatile__ ("" : : : "memory"); -#elif arm_HOST_ARCH && defined(arm_HOST_ARCH_PRE_ARMv7) - __asm__ __volatile__ ("" : : : "memory"); -#elif arm_HOST_ARCH && !defined(arm_HOST_ARCH_PRE_ARMv7) +#elif arm_HOST_ARCH __asm__ __volatile__ ("dmb" : : : "memory"); #elif aarch64_HOST_ARCH __asm__ __volatile__ ("dmb sy" : : : "memory"); |