diff options
| author | Colin Watson <cjwatson@debian.org> | 2014-04-21 22:26:56 -0500 |
|---|---|---|
| committer | Austin Seipp <austin@well-typed.com> | 2014-04-21 22:26:56 -0500 |
| commit | c29bf984dd20431cd4344e8a5c444d7a5be08389 (patch) | |
| tree | f0b0245bdbad8b981ed37d262e28d9977dcb7b35 /includes/stg | |
| parent | a3831391e1defdf69214dc258eebcf37d92991f2 (diff) | |
| download | haskell-c29bf984dd20431cd4344e8a5c444d7a5be08389.tar.gz | |
ghc: initial AArch64 patches
Signed-off-by: Austin Seipp <austin@well-typed.com>
Diffstat (limited to 'includes/stg')
| -rw-r--r-- | includes/stg/HaskellMachRegs.h | 1 | ||||
| -rw-r--r-- | includes/stg/MachRegs.h | 57 |
2 files changed, 57 insertions, 1 deletions
diff --git a/includes/stg/HaskellMachRegs.h b/includes/stg/HaskellMachRegs.h index 94b1612e7b..5480c721fd 100644 --- a/includes/stg/HaskellMachRegs.h +++ b/includes/stg/HaskellMachRegs.h @@ -38,6 +38,7 @@ #define MACHREGS_powerpc (powerpc_TARGET_ARCH || powerpc64_TARGET_ARCH || rs6000_TARGET_ARCH) #define MACHREGS_sparc sparc_TARGET_ARCH #define MACHREGS_arm arm_TARGET_ARCH +#define MACHREGS_aarch64 aarch64_TARGET_ARCH #define MACHREGS_darwin darwin_TARGET_OS #endif diff --git a/includes/stg/MachRegs.h b/includes/stg/MachRegs.h index 587f947a6e..417fb6923b 100644 --- a/includes/stg/MachRegs.h +++ b/includes/stg/MachRegs.h @@ -1,6 +1,6 @@ /* ----------------------------------------------------------------------------- * - * (c) The GHC Team, 1998-2011 + * (c) The GHC Team, 1998-2014 * * Registers used in STG code. Might or might not correspond to * actual machine registers. @@ -531,6 +531,61 @@ #define REG_D2 d11 #endif +/* ----------------------------------------------------------------------------- + The ARMv8/AArch64 ABI register mapping + + The AArch64 provides 31 64-bit general purpose registers + and 32 128-bit SIMD/floating point registers. + + General purpose registers (see Chapter 5.1.1 in ARM IHI 0055B) + + Register | Special | Role in the procedure call standard + ---------+---------+------------------------------------ + SP | | The Stack Pointer + r30 | LR | The Link Register + r29 | FP | The Frame Pointer + r19-r28 | | Callee-saved registers + r18 | | The Platform Register, if needed; + | | or temporary register + r17 | IP1 | The second intra-procedure-call temporary register + r16 | IP0 | The first intra-procedure-call scratch register + r9-r15 | | Temporary registers + r8 | | Indirect result location register + r0-r7 | | Parameter/result registers + + + FPU/SIMD registers + + s/d/q/v0-v7 Argument / result/ scratch registers + s/d/q/v8-v15 callee-saved registers (must be preserved across subrutine calls, + but only bottom 64-bit value needs to be preserved) + s/d/q/v16-v31 temporary registers + + ----------------------------------------------------------------------------- */ + +#elif MACHREGS_aarch64 + +#define REG(x) __asm__(#x) + +#define REG_Base r19 +#define REG_Sp r20 +#define REG_Hp r21 +#define REG_R1 r22 +#define REG_R2 r23 +#define REG_R3 r24 +#define REG_R4 r25 +#define REG_R5 r26 +#define REG_R6 r27 +#define REG_SpLim r28 + +#define REG_F1 s8 +#define REG_F2 s9 +#define REG_F3 s10 +#define REG_F4 s11 + +#define REG_D1 d12 +#define REG_D2 d13 + #else #error Cannot find platform to give register info for |