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| author | Andreas Schwab <schwab@suse.de> | 2020-10-02 23:49:01 +0200 |
|---|---|---|
| committer | Marge Bot <ben+marge-bot@smart-cactus.org> | 2021-03-05 14:01:56 -0500 |
| commit | 31e265c1df948d1bcc82d08affe995fd1d1c1438 (patch) | |
| tree | 4a7cc73979d7276946b7435307359d5a4481d574 /includes/stg | |
| parent | 6141aef49b37297e94c9e33a977438c2de15d086 (diff) | |
| download | haskell-31e265c1df948d1bcc82d08affe995fd1d1c1438.tar.gz | |
Implement riscv64 LLVM backend
This enables a registerised build for the riscv64 architecture.
Diffstat (limited to 'includes/stg')
| -rw-r--r-- | includes/stg/MachRegs.h | 62 | ||||
| -rw-r--r-- | includes/stg/MachRegsForHost.h | 4 | ||||
| -rw-r--r-- | includes/stg/SMP.h | 6 |
3 files changed, 72 insertions, 0 deletions
diff --git a/includes/stg/MachRegs.h b/includes/stg/MachRegs.h index a04452e0e7..4b0991891e 100644 --- a/includes/stg/MachRegs.h +++ b/includes/stg/MachRegs.h @@ -663,6 +663,68 @@ the stack. See Note [Overlapping global registers] for implications. #define CALLER_SAVES_D5 #define CALLER_SAVES_D6 +/* ----------------------------------------------------------------------------- + The riscv64 register mapping + + Register | Role(s) | Call effect + ------------+-----------------------------------------+------------- + zero | Hard-wired zero | - + ra | Return address | caller-saved + sp | Stack pointer | callee-saved + gp | Global pointer | callee-saved + tp | Thread pointer | callee-saved + t0,t1,t2 | - | caller-saved + s0 | Frame pointer | callee-saved + s1 | - | callee-saved + a0,a1 | Arguments / return values | caller-saved + a2..a7 | Arguments | caller-saved + s2..s11 | - | callee-saved + t3..t6 | - | caller-saved + ft0..ft7 | - | caller-saved + fs0,fs1 | - | callee-saved + fa0,fa1 | Arguments / return values | caller-saved + fa2..fa7 | Arguments | caller-saved + fs2..fs11 | - | callee-saved + ft8..ft11 | - | caller-saved + + Each general purpose register as well as each floating-point + register is 64 bits wide. + + -------------------------------------------------------------------------- */ + +#elif defined(MACHREGS_riscv64) + +#define REG(x) __asm__(#x) + +#define REG_Base s1 +#define REG_Sp s2 +#define REG_Hp s3 +#define REG_R1 s4 +#define REG_R2 s5 +#define REG_R3 s6 +#define REG_R4 s7 +#define REG_R5 s8 +#define REG_R6 s9 +#define REG_R7 s10 +#define REG_SpLim s11 + +#define REG_F1 fs0 +#define REG_F2 fs1 +#define REG_F3 fs2 +#define REG_F4 fs3 +#define REG_F5 fs4 +#define REG_F6 fs5 + +#define REG_D1 fs6 +#define REG_D2 fs7 +#define REG_D3 fs8 +#define REG_D4 fs9 +#define REG_D5 fs10 +#define REG_D6 fs11 + +#define MAX_REAL_FLOAT_REG 6 +#define MAX_REAL_DOUBLE_REG 6 + #else #error Cannot find platform to give register info for diff --git a/includes/stg/MachRegsForHost.h b/includes/stg/MachRegsForHost.h index 3597b2be90..e902d528f6 100644 --- a/includes/stg/MachRegsForHost.h +++ b/includes/stg/MachRegsForHost.h @@ -71,6 +71,10 @@ #define MACHREGS_s390x 1 #endif +#if defined(riscv64_HOST_ARCH) +#define MACHREGS_riscv64 1 +#endif + #endif #include "MachRegs.h" diff --git a/includes/stg/SMP.h b/includes/stg/SMP.h index 589bde8266..57eb618592 100644 --- a/includes/stg/SMP.h +++ b/includes/stg/SMP.h @@ -395,6 +395,8 @@ write_barrier(void) { __asm__ __volatile__ ("" : : : "memory"); #elif defined(arm_HOST_ARCH) || defined(aarch64_HOST_ARCH) __asm__ __volatile__ ("dmb st" : : : "memory"); +#elif defined(riscv64_HOST_ARCH) + __asm__ __volatile__ ("fence w,w" : : : "memory"); #else #error memory barriers unimplemented on this architecture #endif @@ -419,6 +421,8 @@ store_load_barrier(void) { __asm__ __volatile__ ("dmb" : : : "memory"); #elif defined(aarch64_HOST_ARCH) __asm__ __volatile__ ("dmb sy" : : : "memory"); +#elif defined(riscv64_HOST_ARCH) + __asm__ __volatile__ ("fence w,r" : : : "memory"); #else #error memory barriers unimplemented on this architecture #endif @@ -444,6 +448,8 @@ load_load_barrier(void) { __asm__ __volatile__ ("dmb" : : : "memory"); #elif defined(aarch64_HOST_ARCH) __asm__ __volatile__ ("dmb sy" : : : "memory"); +#elif defined(riscv64_HOST_ARCH) + __asm__ __volatile__ ("fence w,r" : : : "memory"); #else #error memory barriers unimplemented on this architecture #endif |