Implement PowerPC 64-bit native code backend for Linux

Extend the PowerPC 32-bit native code generator for "64-bit
PowerPC ELF Application Binary Interface Supplement 1.9" by
Ian Lance Taylor and "Power Architecture 64-Bit ELF V2 ABI Specification --
OpenPOWER ABI for Linux Supplement" by IBM.
The latter ABI is mainly used on POWER7/7+ and POWER8
Linux systems running in little-endian mode. The code generator
supports both static and dynamic linking. PowerPC 64-bit
code for ELF ABI 1.9 and 2 is mostly position independent
anyway, and thus so is all the code emitted by the code
generator. In other words, -fPIC does not make a difference.

rts/stg/SMP.h support is implemented.

Following the spirit of the introductory comment in
PPC/CodeGen.hs, the rest of the code is a straightforward
extension of the 32-bit implementation.

Limitations:
* Code is generated only in the medium code model, which
  is also gcc's default
* Local symbols are not accessed directly, which seems to
  also be the case for 32-bit
* LLVM does not work, but this does not work on 32-bit either
* Must use the system runtime linker in GHCi, because the
  GHC linker for "static" object files (rts/Linker.c) for
  PPC 64-bit is not implemented. The system runtime
  (dynamic) linker works.
* The handling of the system stack (register 1) is not ELF-
  compliant so stack traces break. Instead of allocating a new
  stack frame, spill code should use the "official" spill area
  in the current stack frame and deallocation code should restore
  the back chain
* DWARF support is missing

Fixes #9863

Test Plan: validate (on powerpc, too)

Reviewers: simonmar, trofi, erikd, austin

Reviewed By: trofi

Subscribers: bgamari, arnons1, kgardas, thomie

Differential Revision: https://phabricator.haskell.org/D629

GHC Trac Issues: #9863

4 files changed, 32 insertions, 5 deletions

diff --git a/includes/CodeGen.Platform.hs b/includes/CodeGen.Platform.hs
index 1d46a0195b..1ff888af91 100644
--- a/includes/CodeGen.Platform.hs
+++ b/includes/CodeGen.Platform.hs
@@ -881,6 +881,9 @@ freeReg 1 = fastBool False -- The Stack Pointer
 # if !MACHREGS_darwin
 -- most non-darwin powerpc OSes use r2 as a TOC pointer or something like that
 freeReg 2 = fastBool False
+-- TODO: make this conditonal for ppc64 ELF
+freeReg 13 = fastBool False -- reserved for system thread ID
+-- TODO: do not reserve r30 in ppc64 ELF
 -- at least linux in -fPIC relies on r30 in PLT stubs
 freeReg 30 = fastBool False
 # endif
diff --git a/includes/stg/HaskellMachRegs.h b/includes/stg/HaskellMachRegs.h
index 5480c721fd..e95cefd822 100644
--- a/includes/stg/HaskellMachRegs.h
+++ b/includes/stg/HaskellMachRegs.h
@@ -35,7 +35,8 @@
 
 #define MACHREGS_i386     i386_TARGET_ARCH
 #define MACHREGS_x86_64   x86_64_TARGET_ARCH
-#define MACHREGS_powerpc  (powerpc_TARGET_ARCH || powerpc64_TARGET_ARCH || rs6000_TARGET_ARCH)
+#define MACHREGS_powerpc  (powerpc_TARGET_ARCH || powerpc64_TARGET_ARCH \
+                || powerpc64le_TARGET_ARCH || rs6000_TARGET_ARCH)
 #define MACHREGS_sparc    sparc_TARGET_ARCH
 #define MACHREGS_arm      arm_TARGET_ARCH
 #define MACHREGS_aarch64  aarch64_TARGET_ARCH
diff --git a/includes/stg/RtsMachRegs.h b/includes/stg/RtsMachRegs.h
index a9e7b6c439..29262dc17a 100644
--- a/includes/stg/RtsMachRegs.h
+++ b/includes/stg/RtsMachRegs.h
@@ -41,7 +41,8 @@
 
 #define MACHREGS_i386     i386_HOST_ARCH
 #define MACHREGS_x86_64   x86_64_HOST_ARCH
-#define MACHREGS_powerpc  (powerpc_HOST_ARCH || powerpc64_HOST_ARCH || rs6000_HOST_ARCH)
+#define MACHREGS_powerpc  (powerpc_HOST_ARCH || powerpc64_HOST_ARCH \
+        || powerpc64le_HOST_ARCH || rs6000_HOST_ARCH)
 #define MACHREGS_sparc    sparc_HOST_ARCH
 #define MACHREGS_arm      arm_HOST_ARCH
 #define MACHREGS_aarch64  aarch64_HOST_ARCH
diff --git a/includes/stg/SMP.h b/includes/stg/SMP.h
index fbc8bdcfa3..2bc00155c5 100644
--- a/includes/stg/SMP.h
+++ b/includes/stg/SMP.h
@@ -127,6 +127,14 @@ xchg(StgPtr p, StgWord w)
         :"=&r" (result)
         :"r" (w), "r" (p)
     );
+#elif powerpc64_HOST_ARCH || powerpc64le_HOST_ARCH
+    __asm__ __volatile__ (
+        "1:     ldarx     %0, 0, %2\n"
+        "       stdcx.    %1, 0, %2\n"
+        "       bne-      1b"
+        :"=&r" (result)
+        :"r" (w), "r" (p)
+    );
 #elif sparc_HOST_ARCH
     result = w;
     __asm__ __volatile__ (
@@ -208,6 +216,20 @@ cas(StgVolatilePtr p, StgWord o, StgWord n)
         :"cc", "memory"
     );
     return result;
+#elif powerpc64_HOST_ARCH || powerpc64le_HOST_ARCH
+    StgWord result;
+    __asm__ __volatile__ (
+        "1:     ldarx     %0, 0, %3\n"
+        "       cmpd      %0, %1\n"
+        "       bne       2f\n"
+        "       stdcx.    %2, 0, %3\n"
+        "       bne-      1b\n"
+        "2:"
+        :"=&r" (result)
+        :"r" (o), "r" (n), "r" (p)
+        :"cc", "memory"
+    );
+    return result;
 #elif sparc_HOST_ARCH
     __asm__ __volatile__ (
         "cas [%1], %2, %0"
@@ -345,7 +367,7 @@ write_barrier(void) {
     return;
 #elif i386_HOST_ARCH || x86_64_HOST_ARCH
     __asm__ __volatile__ ("" : : : "memory");
-#elif powerpc_HOST_ARCH
+#elif powerpc_HOST_ARCH || powerpc64_HOST_ARCH || powerpc64le_HOST_ARCH
     __asm__ __volatile__ ("lwsync" : : : "memory");
 #elif sparc_HOST_ARCH
     /* Sparc in TSO mode does not require store/store barriers. */
@@ -367,7 +389,7 @@ store_load_barrier(void) {
     __asm__ __volatile__ ("lock; addl $0,0(%%esp)" : : : "memory");
 #elif x86_64_HOST_ARCH
     __asm__ __volatile__ ("lock; addq $0,0(%%rsp)" : : : "memory");
-#elif powerpc_HOST_ARCH
+#elif powerpc_HOST_ARCH || powerpc64_HOST_ARCH || powerpc64le_HOST_ARCH
     __asm__ __volatile__ ("sync" : : : "memory");
 #elif sparc_HOST_ARCH
     __asm__ __volatile__ ("membar #StoreLoad" : : : "memory");
@@ -395,7 +417,7 @@ load_load_barrier(void) {
     __asm__ __volatile__ ("" : : : "memory");
 #elif x86_64_HOST_ARCH
     __asm__ __volatile__ ("" : : : "memory");
-#elif powerpc_HOST_ARCH
+#elif powerpc_HOST_ARCH || powerpc64_HOST_ARCH || powerpc64le_HOST_ARCH
     __asm__ __volatile__ ("lwsync" : : : "memory");
 #elif sparc_HOST_ARCH
     /* Sparc in TSO mode does not require load/load barriers. */