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| author | Karel Gardas <karel.gardas@centrum.cz> | 2011-07-09 17:54:30 +0200 |
|---|---|---|
| committer | Manuel M T Chakravarty <chak@cse.unsw.edu.au> | 2011-08-10 22:03:41 +1000 |
| commit | a9b455c4b6960d47d31e769052104a4a4fc26cf0 (patch) | |
| tree | 6783ad7c5ae85b0ea18a31759e1ead87914733ac /includes | |
| parent | b0538fd43a8d813dff50dbdde493d099b753e0e8 (diff) | |
| download | haskell-a9b455c4b6960d47d31e769052104a4a4fc26cf0.tar.gz | |
RTS: fix xchg/cas fcns to invoke memory barrier on ARMv7 platform
This patch fixes RTS' xchg and cas functions. On ARMv7 it is recommended
to add memory barrier after using ldrex/strex for implementing atomic
lock or operation.
Diffstat (limited to 'includes')
| -rw-r--r-- | includes/stg/SMP.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/includes/stg/SMP.h b/includes/stg/SMP.h index df62e56016..4162058d3b 100644 --- a/includes/stg/SMP.h +++ b/includes/stg/SMP.h @@ -156,6 +156,9 @@ xchg(StgPtr p, StgWord w) " strex %1, %2, [%3]\n" " teq %1, #1\n" " beq 1b\n" +#if !defined(PRE_ARMv7) + " dmb\n" +#endif : "=&r" (result), "=&r" (tmp) : "r" (w), "r" (p) : "memory" @@ -225,6 +228,9 @@ cas(StgVolatilePtr p, StgWord o, StgWord n) " teq %0, #1\n" " it eq\n" " beq 1b\n" +#if !defined(PRE_ARMv7) + " dmb\n" +#endif : "=&r"(tmp), "=&r"(result) : "r"(p), "r"(o), "r"(n) : "cc","memory"); |