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| author | Sergei Trofimovich <siarheit@google.com> | 2015-05-18 22:22:18 +0100 |
|---|---|---|
| committer | Sergei Trofimovich <siarheit@google.com> | 2015-05-18 22:22:34 +0100 |
| commit | eaaa38ba24d5152623cb202a98f71ed09deef0bb (patch) | |
| tree | 78f10f1ecb152e907cf6e7d24ec2c9f748838e1f /includes | |
| parent | 228ddb95ee137e7cef02dcfe2521233892dd61e0 (diff) | |
| download | haskell-eaaa38ba24d5152623cb202a98f71ed09deef0bb.tar.gz | |
includes/stg/SMP.h: implement simple load_/store_load_barrier on armv6 and older
Assuming there is no real SMP systems on these CPUs
I've added only compiler barrier (otherwise write_barrier
and friends need to be fixed as well).
Patch also fixes build breakage reported in #10244.
Signed-off-by: Sergei Trofimovich <siarheit@google.com>
Reviewers: rwbarton, nomeata, austin
Reviewed By: nomeata, austin
Subscribers: bgamari, thomie
Differential Revision: https://phabricator.haskell.org/D894
GHC Trac Issues: #10244
Diffstat (limited to 'includes')
| -rw-r--r-- | includes/stg/SMP.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/includes/stg/SMP.h b/includes/stg/SMP.h index 5ded05d05e..5460a2bd04 100644 --- a/includes/stg/SMP.h +++ b/includes/stg/SMP.h @@ -373,6 +373,8 @@ store_load_barrier(void) { __asm__ __volatile__ ("sync" : : : "memory"); #elif sparc_HOST_ARCH __asm__ __volatile__ ("membar #StoreLoad" : : : "memory"); +#elif arm_HOST_ARCH && defined(arm_HOST_ARCH_PRE_ARMv7) + __asm__ __volatile__ ("" : : : "memory"); #elif arm_HOST_ARCH && !defined(arm_HOST_ARCH_PRE_ARMv7) __asm__ __volatile__ ("dmb" : : : "memory"); #elif aarch64_HOST_ARCH @@ -395,6 +397,8 @@ load_load_barrier(void) { #elif sparc_HOST_ARCH /* Sparc in TSO mode does not require load/load barriers. */ __asm__ __volatile__ ("" : : : "memory"); +#elif arm_HOST_ARCH && defined(arm_HOST_ARCH_PRE_ARMv7) + __asm__ __volatile__ ("" : : : "memory"); #elif arm_HOST_ARCH && !defined(arm_HOST_ARCH_PRE_ARMv7) __asm__ __volatile__ ("dmb" : : : "memory"); #elif aarch64_HOST_ARCH |