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authorAndreas Schwab <schwab@suse.de>2020-10-02 23:49:01 +0200
committerMarge Bot <ben+marge-bot@smart-cactus.org>2021-03-05 14:01:56 -0500
commit31e265c1df948d1bcc82d08affe995fd1d1c1438 (patch)
tree4a7cc73979d7276946b7435307359d5a4481d574 /mk
parent6141aef49b37297e94c9e33a977438c2de15d086 (diff)
downloadhaskell-31e265c1df948d1bcc82d08affe995fd1d1c1438.tar.gz
Implement riscv64 LLVM backend
This enables a registerised build for the riscv64 architecture.
Diffstat (limited to 'mk')
-rw-r--r--mk/config.mk.in2
1 files changed, 1 insertions, 1 deletions
diff --git a/mk/config.mk.in b/mk/config.mk.in
index e2c1591860..9e6c3d8c40 100644
--- a/mk/config.mk.in
+++ b/mk/config.mk.in
@@ -179,7 +179,7 @@ ifeq "$(TargetArch_CPP)" "arm"
# We don't support load/store barriers pre-ARMv7. See #10433.
ArchSupportsSMP=$(if $(filter $(ARM_ISA),ARMv5 ARMv6),NO,YES)
else
-ArchSupportsSMP=$(strip $(patsubst $(TargetArch_CPP), YES, $(findstring $(TargetArch_CPP), i386 x86_64 sparc powerpc powerpc64 powerpc64le s390x aarch64)))
+ArchSupportsSMP=$(strip $(patsubst $(TargetArch_CPP), YES, $(findstring $(TargetArch_CPP), i386 x86_64 sparc powerpc powerpc64 powerpc64le s390x aarch64 riscv64)))
endif
# The THREADED_RTS requires `BaseReg` to be in a register and the