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| author | Ben Gamari <bgamari.foss@gmail.com> | 2017-11-02 17:28:40 -0400 |
|---|---|---|
| committer | Ben Gamari <ben@smart-cactus.org> | 2017-11-02 20:15:47 -0400 |
| commit | 15f788f5e5096641245a4f060600a6db9cbc2c4e (patch) | |
| tree | 99fa80ab340ffc5860eb5abef778c54d68da3e22 /mk | |
| parent | 43537568579a63cb6b8d70b4815d76c46bb9a692 (diff) | |
| download | haskell-15f788f5e5096641245a4f060600a6db9cbc2c4e.tar.gz | |
llvmGen: Pass vector arguments in vector registers by default
Earlier this year Edward Kmett requested [1] that we enable passing of
vector values in vector registers by default. The GHC calling convention
changes have been in LLVM for a number of years now so let's just flip
the switch.
[1] https://mail.haskell.org/pipermail/ghc-devs/2017-March/013905.html
Reviewers: austin
Subscribers: rwbarton, thomie
Differential Revision: https://phabricator.haskell.org/D4142
Diffstat (limited to 'mk')
0 files changed, 0 insertions, 0 deletions