diff options
| author | lrzlin <lrzlin@163.com> | 2022-11-06 14:18:35 +0000 |
|---|---|---|
| committer | Marge Bot <ben+marge-bot@smart-cactus.org> | 2022-12-08 22:46:06 -0500 |
| commit | ea25088d4edd9f96e48f0a7f9407fd8eb9c2ae9c (patch) | |
| tree | 4ec1da1736d0d223403907283139d52228fa56ac /rts/include/stg/SMP.h | |
| parent | d122e02247a371b14c3e906556900c0d600f424d (diff) | |
| download | haskell-ea25088d4edd9f96e48f0a7f9407fd8eb9c2ae9c.tar.gz | |
Add initial support for LoongArch Architecture.
Diffstat (limited to 'rts/include/stg/SMP.h')
| -rw-r--r-- | rts/include/stg/SMP.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/rts/include/stg/SMP.h b/rts/include/stg/SMP.h index b8f72a1248..aaa54e8435 100644 --- a/rts/include/stg/SMP.h +++ b/rts/include/stg/SMP.h @@ -393,6 +393,8 @@ write_barrier(void) { __asm__ __volatile__ ("dmb st" : : : "memory"); #elif defined(riscv64_HOST_ARCH) __asm__ __volatile__ ("fence w,w" : : : "memory"); +#elif defined(loongarch64_HOST_ARCH) + __asm__ __volatile__ ("dbar 0" : : : "memory"); #else #error memory barriers unimplemented on this architecture #endif @@ -417,6 +419,8 @@ store_load_barrier(void) { __asm__ __volatile__ ("dmb sy" : : : "memory"); #elif defined(riscv64_HOST_ARCH) __asm__ __volatile__ ("fence w,r" : : : "memory"); +#elif defined(loongarch64_HOST_ARCH) + __asm__ __volatile__ ("dbar 0" : : : "memory"); #else #error memory barriers unimplemented on this architecture #endif @@ -441,6 +445,8 @@ load_load_barrier(void) { __asm__ __volatile__ ("dmb ld" : : : "memory"); #elif defined(riscv64_HOST_ARCH) __asm__ __volatile__ ("fence r,r" : : : "memory"); +#elif defined(loongarch64_HOST_ARCH) + __asm__ __volatile__ ("dbar 0" : : : "memory"); #else #error memory barriers unimplemented on this architecture #endif |