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| author | Takenobu Tani <takenobu.hs@gmail.com> | 2021-09-04 15:02:42 +0900 |
|---|---|---|
| committer | Takenobu Tani <takenobu.hs@gmail.com> | 2021-11-04 09:40:42 +0000 |
| commit | 6020905a626b52dc383848025cd73f944f68b903 (patch) | |
| tree | 4a01c367bc5def806938c724af0dfdef24b957b3 /rts/include | |
| parent | 1419fb1653b3d440d182efba3844848ff89491f9 (diff) | |
| download | haskell-6020905a626b52dc383848025cd73f944f68b903.tar.gz | |
Correct load_load_barrier for risc-v
This patch corrects the instruction for load_load_barrier().
Current load_load_barrier() incorrectly uses `fence w,r`.
It means a store-load barrier.
See also linux-kernel's smp_rmb() implementation:
https://github.com/torvalds/linux/blob/v5.14/arch/riscv/include/asm/barrier.h#L27
Diffstat (limited to 'rts/include')
| -rw-r--r-- | rts/include/stg/SMP.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/rts/include/stg/SMP.h b/rts/include/stg/SMP.h index de706da290..282680c772 100644 --- a/rts/include/stg/SMP.h +++ b/rts/include/stg/SMP.h @@ -449,7 +449,7 @@ load_load_barrier(void) { #elif defined(aarch64_HOST_ARCH) __asm__ __volatile__ ("dmb sy" : : : "memory"); #elif defined(riscv64_HOST_ARCH) - __asm__ __volatile__ ("fence w,r" : : : "memory"); + __asm__ __volatile__ ("fence r,r" : : : "memory"); #else #error memory barriers unimplemented on this architecture #endif |