Rip out SPARC register support

2 files changed, 0 insertions, 138 deletions

diff --git a/rts/include/stg/MachRegs.h b/rts/include/stg/MachRegs.h
index d50969b66a..6c66e112b2 100644
--- a/rts/include/stg/MachRegs.h
+++ b/rts/include/stg/MachRegs.h
@@ -340,140 +340,6 @@ the stack. See Note [Overlapping global registers] for implications.
 #define MAX_REAL_DOUBLE_REG  6
 
 /* -----------------------------------------------------------------------------
-   The Sun SPARC register mapping
-
-   !! IMPORTANT: if you change this register mapping you must also update
-                 compiler/GHC/CmmToAsm/SPARC/Regs.hs. That file handles the
-                 mapping for the NCG. This one only affects via-c code.
-
-   The SPARC register (window) story: Remember, within the Haskell
-   Threaded World, we essentially ``shut down'' the register-window
-   mechanism---the window doesn't move at all while in this World.  It
-   *does* move, of course, if we call out to arbitrary~C...
-
-   The %i, %l, and %o registers (8 each) are the input, local, and
-   output registers visible in one register window.  The 8 %g (global)
-   registers are visible all the time.
-
-      zero: always zero
-   scratch: volatile across C-fn calls. used by linker.
-       app: usable by application
-    system: reserved for system
-
-     alloc: allocated to in the register allocator, intra-closure only
-
-                GHC usage     v8 ABI        v9 ABI
-   Global
-     %g0        zero        zero          zero
-     %g1        alloc       scratch       scrach
-     %g2        alloc       app           app
-     %g3        alloc       app           app
-     %g4        alloc       app           scratch
-     %g5                    system        scratch
-     %g6                    system        system
-     %g7                    system        system
-
-   Output: can be zapped by callee
-     %o0-o5     alloc       caller saves
-     %o6                    C stack ptr
-     %o7                    C ret addr
-
-   Local: maintained by register windowing mechanism
-     %l0        alloc
-     %l1        R1
-     %l2        R2
-     %l3        R3
-     %l4        R4
-     %l5        R5
-     %l6        alloc
-     %l7        alloc
-
-   Input
-     %i0        Sp
-     %i1        Base
-     %i2        SpLim
-     %i3        Hp
-     %i4        alloc
-     %i5        R6
-     %i6                    C frame ptr
-     %i7                    C ret addr
-
-   The paired nature of the floating point registers causes complications for
-   the native code generator.  For convenience, we pretend that the first 22
-   fp regs %f0 .. %f21 are actually 11 double regs, and the remaining 10 are
-   float (single) regs.  The NCG acts accordingly.  That means that the
-   following FP assignment is rather fragile, and should only be changed
-   with extreme care.  The current scheme is:
-
-      %f0 /%f1    FP return from C
-      %f2 /%f3    D1
-      %f4 /%f5    D2
-      %f6 /%f7    ncg double spill tmp #1
-      %f8 /%f9    ncg double spill tmp #2
-      %f10/%f11   allocatable
-      %f12/%f13   allocatable
-      %f14/%f15   allocatable
-      %f16/%f17   allocatable
-      %f18/%f19   allocatable
-      %f20/%f21   allocatable
-
-      %f22        F1
-      %f23        F2
-      %f24        F3
-      %f25        F4
-      %f26        ncg single spill tmp #1
-      %f27        ncg single spill tmp #2
-      %f28        allocatable
-      %f29        allocatable
-      %f30        allocatable
-      %f31        allocatable
-
-   -------------------------------------------------------------------------- */
-
-#elif defined(MACHREGS_sparc)
-
-#define REG(x) __asm__("%" #x)
-
-#define CALLER_SAVES_USER
-
-#define CALLER_SAVES_F1
-#define CALLER_SAVES_F2
-#define CALLER_SAVES_F3
-#define CALLER_SAVES_F4
-#define CALLER_SAVES_D1
-#define CALLER_SAVES_D2
-
-#define REG_R1          l1
-#define REG_R2          l2
-#define REG_R3          l3
-#define REG_R4          l4
-#define REG_R5          l5
-#define REG_R6          i5
-
-#define REG_F1          f22
-#define REG_F2          f23
-#define REG_F3          f24
-#define REG_F4          f25
-
-/* for each of the double arg regs,
-   Dn_2 is the high half. */
-
-#define REG_D1          f2
-#define REG_D1_2        f3
-
-#define REG_D2          f4
-#define REG_D2_2        f5
-
-#define REG_Sp          i0
-#define REG_SpLim       i2
-
-#define REG_Hp          i3
-
-#define REG_Base        i1
-
-#define NCG_FirstFloatReg f22
-
-/* -----------------------------------------------------------------------------
    The ARM EABI register mapping
 
    Here we consider ARM mode (i.e. 32bit isns)
diff --git a/rts/include/stg/MachRegsForHost.h b/rts/include/stg/MachRegsForHost.h
index e902d528f6..613a0bc4be 100644
--- a/rts/include/stg/MachRegsForHost.h
+++ b/rts/include/stg/MachRegsForHost.h
@@ -51,10 +51,6 @@
 #define MACHREGS_powerpc  1
 #endif
 
-#if defined(sparc_HOST_ARCH)
-#define MACHREGS_sparc    1
-#endif
-
 #if defined(arm_HOST_ARCH)
 #define MACHREGS_arm      1
 #endif