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| author | Cheng Shao <astrohavoc@gmail.com> | 2022-09-09 12:17:41 +0000 |
|---|---|---|
| committer | Marge Bot <ben+marge-bot@smart-cactus.org> | 2022-09-12 07:07:33 -0400 |
| commit | ee471dfb8a4a4bb5131a5baa61d1d0d22c933d5f (patch) | |
| tree | f952d398c9bb0a4973b6627c5530102b8f3849ba /rts | |
| parent | 04062510806e2a3ccf0ecdb71c704a8e1c548c53 (diff) | |
| download | haskell-ee471dfb8a4a4bb5131a5baa61d1d0d22c933d5f.tar.gz | |
rts: fix missing dirty_MVAR argument in stg_writeIOPortzh
Diffstat (limited to 'rts')
| -rw-r--r-- | rts/PrimOps.cmm | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/rts/PrimOps.cmm b/rts/PrimOps.cmm index 7bf403086d..db4d53ea5f 100644 --- a/rts/PrimOps.cmm +++ b/rts/PrimOps.cmm @@ -2246,7 +2246,7 @@ loop: if (q == stg_END_TSO_QUEUE_closure) { /* No takes, the IOPort is now full. */ if (info == stg_MVAR_CLEAN_info) { - ccall dirty_MVAR(BaseReg "ptr", ioport "ptr"); + ccall dirty_MVAR(BaseReg "ptr", ioport "ptr", StgMVar_value(ioport) "ptr"); } StgMVar_value(ioport) = val; |