diff options
Diffstat (limited to 'compiler/GHC/CmmToAsm/Reg/Linear.hs')
| -rw-r--r-- | compiler/GHC/CmmToAsm/Reg/Linear.hs | 16 |
1 files changed, 10 insertions, 6 deletions
diff --git a/compiler/GHC/CmmToAsm/Reg/Linear.hs b/compiler/GHC/CmmToAsm/Reg/Linear.hs index 4d666bc557..8d4da4bd2e 100644 --- a/compiler/GHC/CmmToAsm/Reg/Linear.hs +++ b/compiler/GHC/CmmToAsm/Reg/Linear.hs @@ -122,6 +122,7 @@ import GHC.CmmToAsm.Reg.Liveness import GHC.CmmToAsm.Reg.Utils import GHC.CmmToAsm.Instr import GHC.CmmToAsm.Config +import GHC.CmmToAsm.Types import GHC.Platform.Reg import GHC.Cmm.BlockId @@ -147,7 +148,7 @@ import Control.Applicative -- Allocate registers regAlloc - :: (Outputable instr, Instruction instr) + :: Instruction instr => NCGConfig -> LiveCmmDecl statics instr -> UniqSM ( NatCmmDecl statics instr @@ -204,7 +205,7 @@ regAlloc _ (CmmProc _ _ _ _) -- an entry in the block map or it is the first block. -- linearRegAlloc - :: (Outputable instr, Instruction instr) + :: Instruction instr => NCGConfig -> [BlockId] -- ^ entry points -> BlockMap RegSet @@ -236,7 +237,7 @@ linearRegAlloc config entry_ids block_live sccs -- | Constraints on the instruction instances used by the -- linear allocator. type OutputableRegConstraint freeRegs instr = - (FR freeRegs, Outputable freeRegs, Outputable instr, Instruction instr) + (FR freeRegs, Outputable freeRegs, Instruction instr) linearRegAlloc' :: OutputableRegConstraint freeRegs instr @@ -468,7 +469,10 @@ raInsn block_live new_instrs id (LiveInstr (Instr instr) (Just live)) -- See Note [Unique Determinism and code generation] raInsn _ _ _ instr - = pprPanic "raInsn" (text "no match for:" <> ppr instr) + = do + platform <- getPlatform + let instr' = fmap (pprInstr platform) instr + pprPanic "raInsn" (text "no match for:" <> ppr instr') -- ToDo: what can we do about -- @@ -764,7 +768,7 @@ data SpillLoc = ReadMem StackSlot -- reading from register only in memory -- the list of free registers and free stack slots. allocateRegsAndSpill - :: forall freeRegs instr. (FR freeRegs, Outputable instr, Instruction instr) + :: forall freeRegs instr. (FR freeRegs, Instruction instr) => Bool -- True <=> reading (load up spilled regs) -> [VirtualReg] -- don't push these out -> [instr] -- spill insns @@ -830,7 +834,7 @@ findPrefRealReg vreg = do -- reading is redundant with reason, but we keep it around because it's -- convenient and it maintains the recursive structure of the allocator. -- EZY -allocRegsAndSpill_spill :: (FR freeRegs, Instruction instr, Outputable instr) +allocRegsAndSpill_spill :: (FR freeRegs, Instruction instr) => Bool -> [VirtualReg] -> [instr] |