5 files changed, 6 insertions, 6 deletions
diff --git a/compiler/nativeGen/RegAlloc/Linear/Base.hs b/compiler/nativeGen/RegAlloc/Linear/Base.hs
index ebd31076e3..60d0175c94 100644
--- a/compiler/nativeGen/RegAlloc/Linear/Base.hs
+++ b/compiler/nativeGen/RegAlloc/Linear/Base.hs
@@ -20,8 +20,7 @@ where
 
 import RegAlloc.Linear.FreeRegs
 import RegAlloc.Linear.StackMap
-
-import RegLiveness
+import RegAlloc.Liveness
 import Regs
 
 import Outputable
diff --git a/compiler/nativeGen/RegAlloc/Linear/JoinToTargets.hs b/compiler/nativeGen/RegAlloc/Linear/JoinToTargets.hs
index 5c6334685a..d9e3994b36 100644
--- a/compiler/nativeGen/RegAlloc/Linear/JoinToTargets.hs
+++ b/compiler/nativeGen/RegAlloc/Linear/JoinToTargets.hs
@@ -18,12 +18,12 @@ where
 import RegAlloc.Linear.State
 import RegAlloc.Linear.Base
 import RegAlloc.Linear.FreeRegs
+import RegAlloc.Liveness
 
 import BlockId
 import Instrs
 import Regs
 import RegAllocInfo
-import RegLiveness
 import Cmm	hiding (RegSet)
 
 import Digraph
diff --git a/compiler/nativeGen/RegAlloc/Linear/Main.hs b/compiler/nativeGen/RegAlloc/Linear/Main.hs
index 1d2c78b25f..ce28c4e96e 100644
--- a/compiler/nativeGen/RegAlloc/Linear/Main.hs
+++ b/compiler/nativeGen/RegAlloc/Linear/Main.hs
@@ -96,12 +96,12 @@ import RegAlloc.Linear.StackMap
 import RegAlloc.Linear.FreeRegs
 import RegAlloc.Linear.Stats
 import RegAlloc.Linear.JoinToTargets
+import RegAlloc.Liveness
 
 import BlockId
 import Regs
 import Instrs
 import RegAllocInfo
-import RegLiveness
 import Cmm hiding (RegSet)
 
 import Digraph
diff --git a/compiler/nativeGen/RegAlloc/Linear/State.hs b/compiler/nativeGen/RegAlloc/Linear/State.hs
index a7f49d12d5..94a8f7b52e 100644
--- a/compiler/nativeGen/RegAlloc/Linear/State.hs
+++ b/compiler/nativeGen/RegAlloc/Linear/State.hs
@@ -33,12 +33,12 @@ import RegAlloc.Linear.Stats
 import RegAlloc.Linear.StackMap
 import RegAlloc.Linear.Base
 import RegAlloc.Linear.FreeRegs
+import RegAlloc.Liveness
 
 
 import Instrs
 import Regs
 import RegAllocInfo
-import RegLiveness
 
 import Unique
 import UniqSupply
diff --git a/compiler/nativeGen/RegAlloc/Linear/Stats.hs b/compiler/nativeGen/RegAlloc/Linear/Stats.hs
index c139db731c..95bf8ede82 100644
--- a/compiler/nativeGen/RegAlloc/Linear/Stats.hs
+++ b/compiler/nativeGen/RegAlloc/Linear/Stats.hs
@@ -7,7 +7,8 @@ module RegAlloc.Linear.Stats (
 where
 
 import RegAlloc.Linear.Base
-import RegLiveness
+import RegAlloc.Liveness
+
 import RegAllocInfo
 import Instrs
 import Cmm		(GenBasicBlock(..))