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-rw-r--r--compiler/nativeGen/SPARC/CodeGen/Amode.hs2
-rw-r--r--compiler/nativeGen/SPARC/CodeGen/Base.hs22
-rw-r--r--compiler/nativeGen/SPARC/CodeGen/CondCode.hs4
-rw-r--r--compiler/nativeGen/SPARC/CodeGen/Expand.hs2
-rw-r--r--compiler/nativeGen/SPARC/CodeGen/Gen32.hs64
-rw-r--r--compiler/nativeGen/SPARC/CodeGen/Gen64.hs4
6 files changed, 49 insertions, 49 deletions
diff --git a/compiler/nativeGen/SPARC/CodeGen/Amode.hs b/compiler/nativeGen/SPARC/CodeGen/Amode.hs
index 8d9a303f2f..a59287f171 100644
--- a/compiler/nativeGen/SPARC/CodeGen/Amode.hs
+++ b/compiler/nativeGen/SPARC/CodeGen/Amode.hs
@@ -12,7 +12,7 @@ import SPARC.Instr
import SPARC.Regs
import SPARC.Base
import NCGMonad
-import Size
+import Format
import Cmm
diff --git a/compiler/nativeGen/SPARC/CodeGen/Base.hs b/compiler/nativeGen/SPARC/CodeGen/Base.hs
index 270fd699b0..27b533f46b 100644
--- a/compiler/nativeGen/SPARC/CodeGen/Base.hs
+++ b/compiler/nativeGen/SPARC/CodeGen/Base.hs
@@ -5,7 +5,7 @@ module SPARC.CodeGen.Base (
Amode(..),
Register(..),
- setSizeOfRegister,
+ setFormatOfRegister,
getRegisterReg,
mangleIndexTree
@@ -17,7 +17,7 @@ import SPARC.Instr
import SPARC.Cond
import SPARC.AddrMode
import SPARC.Regs
-import Size
+import Format
import Reg
import CodeGen.Platform
@@ -76,18 +76,18 @@ data Amode
-- Otherwise, the parent can decide which register to put it in.
--
data Register
- = Fixed Size Reg InstrBlock
- | Any Size (Reg -> InstrBlock)
+ = Fixed Format Reg InstrBlock
+ | Any Format (Reg -> InstrBlock)
--- | Change the size field in a Register.
-setSizeOfRegister
- :: Register -> Size -> Register
+-- | Change the format field in a Register.
+setFormatOfRegister
+ :: Register -> Format -> Register
-setSizeOfRegister reg size
+setFormatOfRegister reg format
= case reg of
- Fixed _ reg code -> Fixed size reg code
- Any _ codefn -> Any size codefn
+ Fixed _ reg code -> Fixed format reg code
+ Any _ codefn -> Any format codefn
--------------------------------------------------------------------------------
@@ -95,7 +95,7 @@ setSizeOfRegister reg size
getRegisterReg :: Platform -> CmmReg -> Reg
getRegisterReg _ (CmmLocal (LocalReg u pk))
- = RegVirtual $ mkVirtualReg u (cmmTypeSize pk)
+ = RegVirtual $ mkVirtualReg u (cmmTypeFormat pk)
getRegisterReg platform (CmmGlobal mid)
= case globalRegMaybe platform mid of
diff --git a/compiler/nativeGen/SPARC/CodeGen/CondCode.hs b/compiler/nativeGen/SPARC/CodeGen/CondCode.hs
index cb10830f46..e5fb82df4d 100644
--- a/compiler/nativeGen/SPARC/CodeGen/CondCode.hs
+++ b/compiler/nativeGen/SPARC/CodeGen/CondCode.hs
@@ -14,7 +14,7 @@ import SPARC.Cond
import SPARC.Imm
import SPARC.Base
import NCGMonad
-import Size
+import Format
import Cmm
@@ -98,7 +98,7 @@ condFltCode cond x y = do
code__2 =
if pk1 `cmmEqType` pk2 then
code1 `appOL` code2 `snocOL`
- FCMP True (cmmTypeSize pk1) src1 src2
+ FCMP True (cmmTypeFormat pk1) src1 src2
else if typeWidth pk1 == W32 then
code1 `snocOL` promote src1 `appOL` code2 `snocOL`
FCMP True FF64 tmp src2
diff --git a/compiler/nativeGen/SPARC/CodeGen/Expand.hs b/compiler/nativeGen/SPARC/CodeGen/Expand.hs
index 1d4d1379a5..70cb0111c0 100644
--- a/compiler/nativeGen/SPARC/CodeGen/Expand.hs
+++ b/compiler/nativeGen/SPARC/CodeGen/Expand.hs
@@ -12,7 +12,7 @@ import SPARC.Regs
import SPARC.Ppr ()
import Instruction
import Reg
-import Size
+import Format
import Cmm
diff --git a/compiler/nativeGen/SPARC/CodeGen/Gen32.hs b/compiler/nativeGen/SPARC/CodeGen/Gen32.hs
index 90fb41870d..566cc337b7 100644
--- a/compiler/nativeGen/SPARC/CodeGen/Gen32.hs
+++ b/compiler/nativeGen/SPARC/CodeGen/Gen32.hs
@@ -18,7 +18,7 @@ import SPARC.Imm
import SPARC.Regs
import SPARC.Base
import NCGMonad
-import Size
+import Format
import Reg
import Cmm
@@ -49,7 +49,7 @@ getRegister :: CmmExpr -> NatM Register
getRegister (CmmReg reg)
= do dflags <- getDynFlags
let platform = targetPlatform dflags
- return (Fixed (cmmTypeSize (cmmRegType dflags reg))
+ return (Fixed (cmmTypeFormat (cmmRegType dflags reg))
(getRegisterReg platform reg) nilOL)
getRegister tree@(CmmRegOff _ _)
@@ -115,8 +115,8 @@ getRegister (CmmMachOp mop [x])
-- Integer negation --------------------------------
- MO_S_Neg rep -> trivialUCode (intSize rep) (SUB False False g0) x
- MO_Not rep -> trivialUCode (intSize rep) (XNOR False g0) x
+ MO_S_Neg rep -> trivialUCode (intFormat rep) (SUB False False g0) x
+ MO_Not rep -> trivialUCode (intFormat rep) (XNOR False g0) x
-- Float word size conversion ----------------------
@@ -133,7 +133,7 @@ getRegister (CmmMachOp mop [x])
-- If it's the same size, then nothing needs to be done.
MO_UU_Conv from to
- | from == to -> conversionNop (intSize to) x
+ | from == to -> conversionNop (intFormat to) x
-- To narrow an unsigned word, mask out the high bits to simulate what would
-- happen if we copied the value into a smaller register.
@@ -158,9 +158,9 @@ getRegister (CmmMachOp mop [x])
-- To widen an unsigned word we don't have to do anything.
-- Just leave it in the same register and mark the result as the new size.
- MO_UU_Conv W8 W16 -> conversionNop (intSize W16) x
- MO_UU_Conv W8 W32 -> conversionNop (intSize W32) x
- MO_UU_Conv W16 W32 -> conversionNop (intSize W32) x
+ MO_UU_Conv W8 W16 -> conversionNop (intFormat W16) x
+ MO_UU_Conv W8 W32 -> conversionNop (intFormat W32) x
+ MO_UU_Conv W16 W32 -> conversionNop (intFormat W32) x
-- Signed integer word size conversions ------------
@@ -240,8 +240,8 @@ getRegister (CmmMachOp mop [x, y])
getRegister (CmmLoad mem pk) = do
Amode src code <- getAmode mem
let
- code__2 dst = code `snocOL` LD (cmmTypeSize pk) src dst
- return (Any (cmmTypeSize pk) code__2)
+ code__2 dst = code `snocOL` LD (cmmTypeFormat pk) src dst
+ return (Any (cmmTypeFormat pk) code__2)
getRegister (CmmLit (CmmInt i _))
| fits13Bits i
@@ -289,18 +289,18 @@ integerExtend from to expr
-- arithmetic shift right to sign extend
`snocOL` SRA tmp (RIImm (ImmInt bitCount)) dst
- return (Any (intSize to) code)
+ return (Any (intFormat to) code)
-- | For nop word format conversions we set the resulting value to have the
-- required size, but don't need to generate any actual code.
--
conversionNop
- :: Size -> CmmExpr -> NatM Register
+ :: Format -> CmmExpr -> NatM Register
conversionNop new_rep expr
= do e_code <- getRegister expr
- return (setSizeOfRegister e_code new_rep)
+ return (setFormatOfRegister e_code new_rep)
@@ -477,7 +477,7 @@ trivialCode _ instr x y = do
trivialFCode
:: Width
- -> (Size -> Reg -> Reg -> Reg -> Instr)
+ -> (Format -> Reg -> Reg -> Reg -> Instr)
-> CmmExpr
-> CmmExpr
-> NatM Register
@@ -496,33 +496,33 @@ trivialFCode pk instr x y = do
code__2 dst =
if pk1 `cmmEqType` pk2 then
code1 `appOL` code2 `snocOL`
- instr (floatSize pk) src1 src2 dst
+ instr (floatFormat pk) src1 src2 dst
else if typeWidth pk1 == W32 then
code1 `snocOL` promote src1 `appOL` code2 `snocOL`
instr FF64 tmp src2 dst
else
code1 `appOL` code2 `snocOL` promote src2 `snocOL`
instr FF64 src1 tmp dst
- return (Any (cmmTypeSize $ if pk1 `cmmEqType` pk2 then pk1 else cmmFloat W64)
+ return (Any (cmmTypeFormat $ if pk1 `cmmEqType` pk2 then pk1 else cmmFloat W64)
code__2)
trivialUCode
- :: Size
+ :: Format
-> (RI -> Reg -> Instr)
-> CmmExpr
-> NatM Register
-trivialUCode size instr x = do
+trivialUCode format instr x = do
(src, code) <- getSomeReg x
let
code__2 dst = code `snocOL` instr (RIReg src) dst
- return (Any size code__2)
+ return (Any format code__2)
trivialUFCode
- :: Size
+ :: Format
-> (Reg -> Reg -> Instr)
-> CmmExpr
-> NatM Register
@@ -544,10 +544,10 @@ coerceInt2FP width1 width2 x = do
(src, code) <- getSomeReg x
let
code__2 dst = code `appOL` toOL [
- ST (intSize width1) src (spRel (-2)),
- LD (intSize width1) (spRel (-2)) dst,
- FxTOy (intSize width1) (floatSize width2) dst dst]
- return (Any (floatSize $ width2) code__2)
+ ST (intFormat width1) src (spRel (-2)),
+ LD (intFormat width1) (spRel (-2)) dst,
+ FxTOy (intFormat width1) (floatFormat width2) dst dst]
+ return (Any (floatFormat $ width2) code__2)
@@ -558,26 +558,26 @@ coerceInt2FP width1 width2 x = do
--
coerceFP2Int :: Width -> Width -> CmmExpr -> NatM Register
coerceFP2Int width1 width2 x
- = do let fsize1 = floatSize width1
- fsize2 = floatSize width2
+ = do let fformat1 = floatFormat width1
+ fformat2 = floatFormat width2
- isize2 = intSize width2
+ iformat2 = intFormat width2
(fsrc, code) <- getSomeReg x
- fdst <- getNewRegNat fsize2
+ fdst <- getNewRegNat fformat2
let code2 dst
= code
`appOL` toOL
-- convert float to int format, leaving it in a float reg.
- [ FxTOy fsize1 isize2 fsrc fdst
+ [ FxTOy fformat1 iformat2 fsrc fdst
-- store the int into mem, then load it back to move
-- it into an actual int reg.
- , ST fsize2 fdst (spRel (-2))
- , LD isize2 (spRel (-2)) dst]
+ , ST fformat2 fdst (spRel (-2))
+ , LD iformat2 (spRel (-2)) dst]
- return (Any isize2 code2)
+ return (Any iformat2 code2)
-- | Coerce a double precision floating point value to single precision.
diff --git a/compiler/nativeGen/SPARC/CodeGen/Gen64.hs b/compiler/nativeGen/SPARC/CodeGen/Gen64.hs
index 438deba00a..1942891c77 100644
--- a/compiler/nativeGen/SPARC/CodeGen/Gen64.hs
+++ b/compiler/nativeGen/SPARC/CodeGen/Gen64.hs
@@ -17,7 +17,7 @@ import SPARC.Instr
import SPARC.Ppr()
import NCGMonad
import Instruction
-import Size
+import Format
import Reg
import Cmm
@@ -68,7 +68,7 @@ assignReg_I64Code (CmmLocal (LocalReg u_dst pk)) valueTree
= do
ChildCode64 vcode r_src_lo <- iselExpr64 valueTree
let
- r_dst_lo = RegVirtual $ mkVirtualReg u_dst (cmmTypeSize pk)
+ r_dst_lo = RegVirtual $ mkVirtualReg u_dst (cmmTypeFormat pk)
r_dst_hi = getHiVRegFromLo r_dst_lo
r_src_hi = getHiVRegFromLo r_src_lo
mov_lo = mkMOV r_src_lo r_dst_lo
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