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-rw-r--r--compiler/nativeGen/SPARC/Ppr.hs14
-rw-r--r--compiler/nativeGen/SPARC/Regs.hs2
2 files changed, 11 insertions, 5 deletions
diff --git a/compiler/nativeGen/SPARC/Ppr.hs b/compiler/nativeGen/SPARC/Ppr.hs
index aa355f97cb..fc67f77541 100644
--- a/compiler/nativeGen/SPARC/Ppr.hs
+++ b/compiler/nativeGen/SPARC/Ppr.hs
@@ -45,6 +45,7 @@ import CLabel
import Hoopl.Label
import Hoopl.Collections
+import Unique ( pprUniqueAlways )
import Outputable
import GHC.Platform
import FastString
@@ -147,7 +148,12 @@ pprReg :: Reg -> SDoc
pprReg reg
= case reg of
RegVirtual vr
- -> ppr vr
+ -> case vr of
+ VirtualRegI u -> text "%vI_" <> pprUniqueAlways u
+ VirtualRegHi u -> text "%vHi_" <> pprUniqueAlways u
+ VirtualRegF u -> text "%vF_" <> pprUniqueAlways u
+ VirtualRegD u -> text "%vD_" <> pprUniqueAlways u
+
RegReal rr
-> case rr of
@@ -215,8 +221,7 @@ pprFormat x
II32 -> sLit ""
II64 -> sLit "d"
FF32 -> sLit ""
- FF64 -> sLit "d"
- VecFormat _ _ _ -> panic "SPARC.Ppr.pprFormat: VecFormat")
+ FF64 -> sLit "d")
-- | Pretty print a format for an instruction suffix.
@@ -230,8 +235,7 @@ pprStFormat x
II32 -> sLit ""
II64 -> sLit "x"
FF32 -> sLit ""
- FF64 -> sLit "d"
- VecFormat _ _ _ -> panic "SPARC.Ppr.pprFormat: VecFormat")
+ FF64 -> sLit "d")
diff --git a/compiler/nativeGen/SPARC/Regs.hs b/compiler/nativeGen/SPARC/Regs.hs
index e46dbd0d38..0d7edc346a 100644
--- a/compiler/nativeGen/SPARC/Regs.hs
+++ b/compiler/nativeGen/SPARC/Regs.hs
@@ -104,6 +104,7 @@ virtualRegSqueeze cls vr
VirtualRegD{} -> 1
_other -> 0
+
{-# INLINE realRegSqueeze #-}
realRegSqueeze :: RegClass -> RealReg -> Int
@@ -133,6 +134,7 @@ realRegSqueeze cls rr
RealRegPair{} -> 1
+
-- | All the allocatable registers in the machine,
-- including register pairs.
allRealRegs :: [RealReg]