9 files changed, 10 insertions, 10 deletions
diff --git a/compiler/nativeGen/BlockLayout.hs b/compiler/nativeGen/BlockLayout.hs
index d8b844c32b..45779d8089 100644
--- a/compiler/nativeGen/BlockLayout.hs
+++ b/compiler/nativeGen/BlockLayout.hs
@@ -79,7 +79,7 @@ import Control.Monad (foldM)
   Edge weights not only represent likelyhood of control transfer between blocks
   but also how much a block would benefit from being placed sequentially after
   it's predecessor.
-  For example blocks which are preceeded by an info table are more likely to end
+  For example blocks which are preceded by an info table are more likely to end
   up in a different cache line than their predecessor and we can't eliminate the jump
   so there is less benefit to placing them sequentially.
 
diff --git a/compiler/nativeGen/Format.hs b/compiler/nativeGen/Format.hs
index 31472893e7..745d1e7b65 100644
--- a/compiler/nativeGen/Format.hs
+++ b/compiler/nativeGen/Format.hs
@@ -3,7 +3,7 @@
 --
 --      TODO:   Signed vs unsigned?
 --
---      TODO:   This module is currenly shared by all architectures because
+--      TODO:   This module is currently shared by all architectures because
 --              NCGMonad need to know about it to make a VReg. It would be better
 --              to have architecture specific formats, and do the overloading
 --              properly. eg SPARC doesn't care about FF80.
diff --git a/compiler/nativeGen/PIC.hs b/compiler/nativeGen/PIC.hs
index 7ea68e1105..a38f3fa18f 100644
--- a/compiler/nativeGen/PIC.hs
+++ b/compiler/nativeGen/PIC.hs
@@ -420,7 +420,7 @@ picRelative dflags arch OSDarwin lbl
 
 -- On AIX we use an indirect local TOC anchored by 'gotLabel'.
 -- This way we use up only one global TOC entry per compilation-unit
--- (this is quite similiar to GCC's @-mminimal-toc@ compilation mode)
+-- (this is quite similar to GCC's @-mminimal-toc@ compilation mode)
 picRelative dflags _ OSAIX lbl
         = CmmLabelDiffOff lbl gotLabel 0 (wordWidth dflags)
 
@@ -623,7 +623,7 @@ pprImportedSymbol _ (Platform { platformMini = PlatformMini { platformMini_os =
 
 -- XCOFF / AIX
 --
--- Similiar to PPC64 ELF v1, there's dedicated TOC register (r2). To
+-- Similar to PPC64 ELF v1, there's dedicated TOC register (r2). To
 -- workaround the limitation of a global TOC we use an indirect TOC
 -- with the label `ghc_toc_table`.
 --
diff --git a/compiler/nativeGen/PPC/CodeGen.hs b/compiler/nativeGen/PPC/CodeGen.hs
index 5f852973ae..ea663dcc23 100644
--- a/compiler/nativeGen/PPC/CodeGen.hs
+++ b/compiler/nativeGen/PPC/CodeGen.hs
@@ -1690,7 +1690,7 @@ genCCall' dflags gcp target dest_regs args
                        `appOL`  codeAfter)
                      GCPAIX          -> return ( dynCode
                        -- AIX/XCOFF follows the PowerOPEN ABI
-                       -- which is quite similiar to LinuxPPC64/ELFv1
+                       -- which is quite similar to LinuxPPC64/ELFv1
                        `appOL`  codeBefore
                        `snocOL` ST spFormat toc (AddrRegImm sp (ImmInt 20))
                        `snocOL` LD II32 r11 (AddrRegImm dynReg (ImmInt 0))
diff --git a/compiler/nativeGen/RegAlloc/Graph/Spill.hs b/compiler/nativeGen/RegAlloc/Graph/Spill.hs
index eccc83eb48..22a88c02c0 100644
--- a/compiler/nativeGen/RegAlloc/Graph/Spill.hs
+++ b/compiler/nativeGen/RegAlloc/Graph/Spill.hs
@@ -297,7 +297,7 @@ patchInstr
 patchInstr reg instr
  = do   nUnique         <- newUnique
 
-        -- The register we're rewriting is suppoed to be virtual.
+        -- The register we're rewriting is supposed to be virtual.
         -- If it's not then something has gone horribly wrong.
         let nReg
              = case reg of
diff --git a/compiler/nativeGen/RegAlloc/Graph/SpillCost.hs b/compiler/nativeGen/RegAlloc/Graph/SpillCost.hs
index 52f590948a..4be25a71ba 100644
--- a/compiler/nativeGen/RegAlloc/Graph/SpillCost.hs
+++ b/compiler/nativeGen/RegAlloc/Graph/SpillCost.hs
@@ -297,7 +297,7 @@ nodeDegree classOfVirtualReg graph reg
 
 
 -- | Show a spill cost record, including the degree from the graph
---   and final calulated spill cost.
+--   and final calculated spill cost.
 pprSpillCostRecord
         :: (VirtualReg -> RegClass)
         -> (Reg -> SDoc)
diff --git a/compiler/nativeGen/RegClass.hs b/compiler/nativeGen/RegClass.hs
index fbbb786817..f4170cca94 100644
--- a/compiler/nativeGen/RegClass.hs
+++ b/compiler/nativeGen/RegClass.hs
@@ -12,7 +12,7 @@ import  Unique
 
 -- | The class of a register.
 --      Used in the register allocator.
---      We treat all registers in a class as being interchangable.
+--      We treat all registers in a class as being interchangeable.
 --
 data RegClass
         = RcInteger
diff --git a/compiler/nativeGen/SPARC/CodeGen/Expand.hs b/compiler/nativeGen/SPARC/CodeGen/Expand.hs
index a29c24dcd4..237311956e 100644
--- a/compiler/nativeGen/SPARC/CodeGen/Expand.hs
+++ b/compiler/nativeGen/SPARC/CodeGen/Expand.hs
@@ -51,7 +51,7 @@ expandBlockInstrs (ii:is)
 
 
 -- | In the SPARC instruction set the FP register pairs that are used
---      to hold 64 bit floats are refered to by just the first reg
+--      to hold 64 bit floats are referred to by just the first reg
 --      of the pair. Remap our internal reg pairs to the appropriate reg.
 --
 --      For example:
diff --git a/compiler/nativeGen/X86/Instr.hs b/compiler/nativeGen/X86/Instr.hs
index 7e47860143..80a2c8b28e 100644
--- a/compiler/nativeGen/X86/Instr.hs
+++ b/compiler/nativeGen/X86/Instr.hs
@@ -816,7 +816,7 @@ x86_mkJumpInstr id
 --                         |                   |
 --                         +-------------------+
 --
---   In essense each allocation larger than a page size needs to be chunked and
+--   In essence each allocation larger than a page size needs to be chunked and
 --   a probe emitted after each page allocation.  You have to hit the guard
 --   page so the kernel can map in the next page, otherwise you'll segfault.
 --