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-rw-r--r--includes/CodeGen.Platform.hs79
-rw-r--r--includes/stg/MachRegs.h2
-rw-r--r--includes/stg/RtsMachRegs.h1
-rw-r--r--includes/stg/SMP.h37
4 files changed, 116 insertions, 3 deletions
diff --git a/includes/CodeGen.Platform.hs b/includes/CodeGen.Platform.hs
index 62708cc4cc..9916e0ef71 100644
--- a/includes/CodeGen.Platform.hs
+++ b/includes/CodeGen.Platform.hs
@@ -99,7 +99,12 @@ import Reg
# define zmm14 70
# define zmm15 71
-#elif MACHREGS_powerpc
+-- Note: these are only needed for ARM/ARM64 because globalRegMaybe is now used in CmmSink.hs.
+-- Since it's only used to check 'isJust', the actual values don't matter, thus
+-- I'm not sure if these are the correct numberings.
+-- Normally, the register names are just stringified as part of the REG() macro
+
+#elif MACHREGS_powerpc || MACHREGS_arm || MACHREGS_aarch64
# define r0 0
# define r1 1
@@ -134,6 +139,76 @@ import Reg
# define r30 30
# define r31 31
+-- See note above. These aren't actually used for anything except satisfying the compiler for globalRegMaybe
+-- so I'm unsure if they're the correct numberings, should they ever be attempted to be used in the NCG.
+#if MACHREGS_aarch64 || MACHREGS_arm
+# define s0 32
+# define s1 33
+# define s2 34
+# define s3 35
+# define s4 36
+# define s5 37
+# define s6 38
+# define s7 39
+# define s8 40
+# define s9 41
+# define s10 42
+# define s11 43
+# define s12 44
+# define s13 45
+# define s14 46
+# define s15 47
+# define s16 48
+# define s17 49
+# define s18 50
+# define s19 51
+# define s20 52
+# define s21 53
+# define s22 54
+# define s23 55
+# define s24 56
+# define s25 57
+# define s26 58
+# define s27 59
+# define s28 60
+# define s29 61
+# define s30 62
+# define s31 63
+
+# define d0 32
+# define d1 33
+# define d2 34
+# define d3 35
+# define d4 36
+# define d5 37
+# define d6 38
+# define d7 39
+# define d8 40
+# define d9 41
+# define d10 42
+# define d11 43
+# define d12 44
+# define d13 45
+# define d14 46
+# define d15 47
+# define d16 48
+# define d17 49
+# define d18 50
+# define d19 51
+# define d20 52
+# define d21 53
+# define d22 54
+# define d23 55
+# define d24 56
+# define d25 57
+# define d26 58
+# define d27 59
+# define d28 60
+# define d29 61
+# define d30 62
+# define d31 63
+#endif
+
# if MACHREGS_darwin
# define f0 32
# define f1 33
@@ -557,7 +632,7 @@ haveRegBase = False
-- in a real machine register, otherwise returns @'Just' reg@, where
-- reg is the machine register it is stored in.
globalRegMaybe :: GlobalReg -> Maybe RealReg
-#if MACHREGS_i386 || MACHREGS_x86_64 || MACHREGS_sparc || MACHREGS_powerpc
+#if MACHREGS_i386 || MACHREGS_x86_64 || MACHREGS_sparc || MACHREGS_powerpc || MACHREGS_arm || MACHREGS_aarch64
# ifdef REG_Base
globalRegMaybe BaseReg = Just (RealRegSingle REG_Base)
# endif
diff --git a/includes/stg/MachRegs.h b/includes/stg/MachRegs.h
index 417fb6923b..3eeb697604 100644
--- a/includes/stg/MachRegs.h
+++ b/includes/stg/MachRegs.h
@@ -585,6 +585,8 @@
#define REG_D1 d12
#define REG_D2 d13
+#define REG_D3 d14
+#define REG_D4 d15
#else
diff --git a/includes/stg/RtsMachRegs.h b/includes/stg/RtsMachRegs.h
index 130221359d..a9e7b6c439 100644
--- a/includes/stg/RtsMachRegs.h
+++ b/includes/stg/RtsMachRegs.h
@@ -44,6 +44,7 @@
#define MACHREGS_powerpc (powerpc_HOST_ARCH || powerpc64_HOST_ARCH || rs6000_HOST_ARCH)
#define MACHREGS_sparc sparc_HOST_ARCH
#define MACHREGS_arm arm_HOST_ARCH
+#define MACHREGS_aarch64 aarch64_HOST_ARCH
#define MACHREGS_darwin darwin_HOST_OS
#endif
diff --git a/includes/stg/SMP.h b/includes/stg/SMP.h
index 76daddef15..732ac5364b 100644
--- a/includes/stg/SMP.h
+++ b/includes/stg/SMP.h
@@ -157,6 +157,19 @@ xchg(StgPtr p, StgWord w)
: "r" (w), "r" (p)
: "memory"
);
+#elif aarch64_HOST_ARCH
+ // Don't think we actually use tmp here, but leaving
+ // it for consistent numbering
+ StgWord tmp;
+ __asm__ __volatile__ (
+ "1: ldaxr %0, [%3]\n"
+ " stlxr %w0, %2, [%3]\n"
+ " cbnz %w0, 1b\n"
+ " dmb sy\n"
+ : "=&r" (result), "=&r" (tmp)
+ : "r" (w), "r" (p)
+ : "memory"
+ );
#else
#error xchg() unimplemented on this architecture
#endif
@@ -232,6 +245,24 @@ cas(StgVolatilePtr p, StgWord o, StgWord n)
: "cc","memory");
return result;
+#elif aarch64_HOST_ARCH
+ // Don't think we actually use tmp here, but leaving
+ // it for consistent numbering
+ StgWord result,tmp;
+
+ __asm__ __volatile__(
+ "1: ldxr %1, [%2]\n"
+ " mov %w0, #0\n"
+ " cmp %1, %3\n"
+ " b.ne 2f\n"
+ " stxr %w0, %4, [%2]\n"
+ " cbnz %w0, 1b\n"
+ "2: dmb sy\n"
+ : "=&r"(tmp), "=&r"(result)
+ : "r"(p), "r"(o), "r"(n)
+ : "cc","memory");
+
+ return result;
#else
#error cas() unimplemented on this architecture
#endif
@@ -313,7 +344,7 @@ write_barrier(void) {
__asm__ __volatile__ ("" : : : "memory");
#elif arm_HOST_ARCH && defined(arm_HOST_ARCH_PRE_ARMv7)
__asm__ __volatile__ ("" : : : "memory");
-#elif arm_HOST_ARCH && !defined(arm_HOST_ARCH_PRE_ARMv7)
+#elif (arm_HOST_ARCH && !defined(arm_HOST_ARCH_PRE_ARMv7)) || aarch64_HOST_ARCH
__asm__ __volatile__ ("dmb st" : : : "memory");
#else
#error memory barriers unimplemented on this architecture
@@ -334,6 +365,8 @@ store_load_barrier(void) {
__asm__ __volatile__ ("membar #StoreLoad" : : : "memory");
#elif arm_HOST_ARCH && !defined(arm_HOST_ARCH_PRE_ARMv7)
__asm__ __volatile__ ("dmb" : : : "memory");
+#elif aarch64_HOST_ARCH
+ __asm__ __volatile__ ("dmb sy" : : : "memory");
#else
#error memory barriers unimplemented on this architecture
#endif
@@ -354,6 +387,8 @@ load_load_barrier(void) {
__asm__ __volatile__ ("" : : : "memory");
#elif arm_HOST_ARCH && !defined(arm_HOST_ARCH_PRE_ARMv7)
__asm__ __volatile__ ("dmb" : : : "memory");
+#elif aarch64_HOST_ARCH
+ __asm__ __volatile__ ("dmb sy" : : : "memory");
#else
#error memory barriers unimplemented on this architecture
#endif
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