Commit message (Expand) | Author | Age | Files | Lines | |
---|---|---|---|---|---|
* | DynFlags: disentangle Outputable | Sylvain Henry | 2020-08-12 | 1 | -0/+1 |
* | Refactor linear reg alloc to remember past assignments. | Andreas Klebinger | 2020-05-21 | 1 | -0/+4 |
* | Modules: Utils and Data (#13009) | Sylvain Henry | 2020-04-26 | 1 | -2/+2 |
* | Modules: CmmToAsm (#13009) | Sylvain Henry | 2020-02-24 | 1 | -0/+188 |