From 303776ab1ff8e192fe42374c8547b7c77305796e Mon Sep 17 00:00:00 2001 From: Jan Stolarek Date: Wed, 5 Nov 2014 13:44:32 +0100 Subject: Update User's Guide, cleanup DynFlags --- compiler/cmm/CmmCallConv.hs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'compiler/cmm/CmmCallConv.hs') diff --git a/compiler/cmm/CmmCallConv.hs b/compiler/cmm/CmmCallConv.hs index f36fc0bae5..440ee5634f 100644 --- a/compiler/cmm/CmmCallConv.hs +++ b/compiler/cmm/CmmCallConv.hs @@ -106,7 +106,7 @@ passFloatArgsInXmm dflags = case platformArch (targetPlatform dflags) of -- On X86_64, we always pass 128-bit-wide vectors in registers. On 32-bit X86 -- and for all larger vector sizes on X86_64, LLVM's GHC calling convention --- doesn't currently passing vectors in registers. The patch to update the GHC +-- does not currently pass vectors in registers. The patch to update the GHC -- calling convention to support passing SIMD vectors in registers is small and -- well-contained, so it may make it into LLVM 3.4. The hidden -- -fllvm-pass-vectors-in-regs flag will generate LLVM code that attempts to -- cgit v1.2.1