From ea25088d4edd9f96e48f0a7f9407fd8eb9c2ae9c Mon Sep 17 00:00:00 2001
From: lrzlin <lrzlin@163.com>
Date: Sun, 6 Nov 2022 14:18:35 +0000
Subject: Add initial support for LoongArch Architecture.

---
 rts/include/stg/MachRegs.h        | 51 +++++++++++++++++++++++++++++++++++++++
 rts/include/stg/MachRegsForHost.h |  4 +++
 rts/include/stg/SMP.h             |  6 +++++
 3 files changed, 61 insertions(+)

(limited to 'rts/include')

diff --git a/rts/include/stg/MachRegs.h b/rts/include/stg/MachRegs.h
index 2563f938ca..f0253865ea 100644
--- a/rts/include/stg/MachRegs.h
+++ b/rts/include/stg/MachRegs.h
@@ -626,6 +626,57 @@ the stack. See Note [Overlapping global registers] for implications.
 #define REG_HpLim          27
 #define REG_CCCS           28
 
+/* -----------------------------------------------------------------------------
+   The loongarch64 register mapping
+
+   Register    | Role(s)                                 | Call effect
+   ------------+-----------------------------------------+-------------
+   zero        | Hard-wired zero                         | -
+   ra          | Return address                          | caller-saved
+   tp          | Thread pointer                          | -
+   sp          | Stack pointer                           | callee-saved
+   a0,a1       | Arguments / return values               | caller-saved
+   a2..a7      | Arguments                               | caller-saved
+   t0..t8      | -                                       | caller-saved
+   u0          | Reserve                                 | -
+   fp          | Frame pointer                           | callee-saved
+   s0..s8      | -                                       | callee-saved
+   fa0,fa1     | Arguments / return values               | caller-saved
+   fa2..fa7    | Arguments                               | caller-saved
+   ft0..ft15   | -                                       | caller-saved
+   fs0..fs7    | -                                       | callee-saved
+
+   Each general purpose register as well as each floating-point
+   register is 64 bits wide, also, the u0 register is called r21 in some cases.
+
+   -------------------------------------------------------------------------- */
+#elif defined(MACHREGS_loongarch64)
+
+#define REG(x) __asm__("$" #x)
+
+#define REG_Base        s0
+#define REG_Sp          s1
+#define REG_Hp          s2
+#define REG_R1          s3
+#define REG_R2          s4
+#define REG_R3          s5
+#define REG_R4          s6
+#define REG_R5          s7
+#define REG_SpLim       s8
+
+#define REG_F1          fs0
+#define REG_F2          fs1
+#define REG_F3          fs2
+#define REG_F4          fs3
+
+#define REG_D1          fs4
+#define REG_D2          fs5
+#define REG_D3          fs6
+#define REG_D4          fs7
+
+#define MAX_REAL_FLOAT_REG   4
+#define MAX_REAL_DOUBLE_REG  4
+
 #else
 
 #error Cannot find platform to give register info for
diff --git a/rts/include/stg/MachRegsForHost.h b/rts/include/stg/MachRegsForHost.h
index 78f823d95c..6452df4158 100644
--- a/rts/include/stg/MachRegsForHost.h
+++ b/rts/include/stg/MachRegsForHost.h
@@ -79,6 +79,10 @@
 #define MACHREGS_NO_REGS 1
 #endif
 
+#if defined(loongarch64_HOST_ARCH)
+#define MACHREGS_loongarch64  1
+#endif
+
 #endif
 
 #include "MachRegs.h"
diff --git a/rts/include/stg/SMP.h b/rts/include/stg/SMP.h
index b8f72a1248..aaa54e8435 100644
--- a/rts/include/stg/SMP.h
+++ b/rts/include/stg/SMP.h
@@ -393,6 +393,8 @@ write_barrier(void) {
     __asm__ __volatile__ ("dmb  st" : : : "memory");
 #elif defined(riscv64_HOST_ARCH)
     __asm__ __volatile__ ("fence w,w" : : : "memory");
+#elif defined(loongarch64_HOST_ARCH)
+    __asm__ __volatile__ ("dbar 0" : : : "memory");
 #else
 #error memory barriers unimplemented on this architecture
 #endif
@@ -417,6 +419,8 @@ store_load_barrier(void) {
     __asm__ __volatile__ ("dmb sy" : : : "memory");
 #elif defined(riscv64_HOST_ARCH)
     __asm__ __volatile__ ("fence w,r" : : : "memory");
+#elif defined(loongarch64_HOST_ARCH)
+    __asm__ __volatile__ ("dbar 0" : : : "memory");
 #else
 #error memory barriers unimplemented on this architecture
 #endif
@@ -441,6 +445,8 @@ load_load_barrier(void) {
     __asm__ __volatile__ ("dmb ld" : : : "memory");
 #elif defined(riscv64_HOST_ARCH)
     __asm__ __volatile__ ("fence r,r" : : : "memory");
+#elif defined(loongarch64_HOST_ARCH)
+    __asm__ __volatile__ ("dbar 0" : : : "memory");
 #else
 #error memory barriers unimplemented on this architecture
 #endif
-- 
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