blob: 49596274221a55301c93e8466f06be3fd1174c5c (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
|
{-# GHC_PRAGMA INTERFACE VERSION 5 #-}
interface AsmRegAlloc where
import CLabelInfo(CLabel)
import FiniteMap(FiniteMap)
import OrdList(OrdList)
import Outputable(NamedThing, Outputable)
import PrimKind(PrimKind)
import UniqFM(UniqFM)
import UniqSet(UniqSet(..))
import Unique(Unique)
class MachineCode a where
regUsage :: a -> RegUsage
regLiveness :: a -> RegLiveness -> RegLiveness
patchRegs :: a -> (Reg -> Reg) -> a
spillReg :: Reg -> Reg -> OrdList a
loadReg :: Reg -> Reg -> OrdList a
class MachineRegisters a where
mkMRegs :: [Int] -> a
possibleMRegs :: PrimKind -> a -> [Int]
useMReg :: a -> Int# -> a
useMRegs :: a -> [Int] -> a
freeMReg :: a -> Int# -> a
freeMRegs :: a -> [Int] -> a
data CLabel
data FiniteMap a b
data FutureLive = FL (UniqFM Reg) (FiniteMap CLabel (UniqFM Reg))
data OrdList a
data PrimKind
data Reg = FixedReg Int# | MappedReg Int# | MemoryReg Int PrimKind | UnmappedReg Unique PrimKind
data RegLiveness = RL (UniqFM Reg) FutureLive
data RegUsage = RU (UniqFM Reg) (UniqFM Reg)
data UniqFM a
type UniqSet a = UniqFM a
data Unique
extractMappedRegNos :: [Reg] -> [Int]
mkReg :: Unique -> PrimKind -> Reg
runHairyRegAllocate :: (MachineRegisters a, MachineCode b) => a -> [Int] -> OrdList b -> [b]
runRegAllocate :: (MachineRegisters a, MachineCode b) => a -> [Int] -> OrdList b -> [b]
instance Eq Reg
instance Ord Reg
instance NamedThing Reg
instance Outputable Reg
instance Text Reg
|