2009-05-27 Hans Boehm <Hans.Boehm@hp.com> (Really Ivan Maidanski)gc7_2alpha2

	(diff87_cvs, resembling diff29, diff68, diff78 partly)
	* doc/README.txt: Remove outdated info about Windows support.
	* src/atomic_ops/generalize.h (AO_nop_full): Replace
	K&R-style function definition with ANSI C one.
	* src/atomic_ops/sysdeps/armcc/arm_v6.h (AO_nop_full): Ditto.
	* src/atomic_ops/sysdeps/gcc/alpha.h (AO_nop_full, AO_nop_write):
	Ditto.
	* src/atomic_ops/sysdeps/gcc/arm.h (AO_nop_full): Ditto.
	* src/atomic_ops/sysdeps/gcc/ia64.h (AO_nop_full): Ditto.
	* src/atomic_ops/sysdeps/gcc/mips.h (AO_nop_full): Ditto.
	* src/atomic_ops/sysdeps/gcc/powerpc.h (AO_nop_full, AO_lwsync): Ditto.
	* src/atomic_ops/sysdeps/gcc/x86.h (AO_nop_full): Ditto.
	* src/atomic_ops/sysdeps/generic_pthread.h (AO_nop_full): Ditto.
	* src/atomic_ops/sysdeps/hpc/ia64.h (AO_nop_full): Ditto.
	* src/atomic_ops/sysdeps/icc/ia64.h (AO_nop_full): Ditto.
	* src/atomic_ops/sysdeps/ordered.h (AO_nop_full): Ditto.
	* src/atomic_ops/sysdeps/ordered_except_wr.h (AO_nop_write): Ditto.
	* src/atomic_ops/sysdeps/read_ordered.h (AO_nop_read): Ditto.
	* src/atomic_ops/sysdeps/test_and_set_t_is_ao_t.h (AO_TS_val): Fix
	comment.

17 files changed, 40 insertions, 22 deletions

diff --git a/ChangeLog b/ChangeLog
index 68d7d9f..bf85ced 100644
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,3 +1,25 @@
+2009-05-27 Hans Boehm <Hans.Boehm@hp.com> (Really Ivan Maidanski)
+	(diff87_cvs, resembling diff29, diff68, diff78 partly)
+	* doc/README.txt: Remove outdated info about Windows support.
+	* src/atomic_ops/generalize.h (AO_nop_full): Replace
+	K&R-style function definition with ANSI C one.
+	* src/atomic_ops/sysdeps/armcc/arm_v6.h (AO_nop_full): Ditto.
+	* src/atomic_ops/sysdeps/gcc/alpha.h (AO_nop_full, AO_nop_write):
+	Ditto.
+	* src/atomic_ops/sysdeps/gcc/arm.h (AO_nop_full): Ditto.
+	* src/atomic_ops/sysdeps/gcc/ia64.h (AO_nop_full): Ditto.
+	* src/atomic_ops/sysdeps/gcc/mips.h (AO_nop_full): Ditto.
+	* src/atomic_ops/sysdeps/gcc/powerpc.h (AO_nop_full, AO_lwsync): Ditto.
+	* src/atomic_ops/sysdeps/gcc/x86.h (AO_nop_full): Ditto.
+	* src/atomic_ops/sysdeps/generic_pthread.h (AO_nop_full): Ditto.
+	* src/atomic_ops/sysdeps/hpc/ia64.h (AO_nop_full): Ditto.
+	* src/atomic_ops/sysdeps/icc/ia64.h (AO_nop_full): Ditto.
+	* src/atomic_ops/sysdeps/ordered.h (AO_nop_full): Ditto.
+	* src/atomic_ops/sysdeps/ordered_except_wr.h (AO_nop_write): Ditto.
+	* src/atomic_ops/sysdeps/read_ordered.h (AO_nop_read): Ditto.
+	* src/atomic_ops/sysdeps/test_and_set_t_is_ao_t.h (AO_TS_val): Fix
+	comment.
+	
 2009-02-24 Hans Boehm <Hans.Boehm@hp.com> (Really primarily Earl Chew)
 	* src/atomic_ops/sysdeps/gcc/powerpc.h: Add index,
 	update modifiers to asms, refine clobbers to "cr0", use
diff --git a/doc/README.txt b/doc/README.txt
index 12c5856..29c8597 100644
--- a/doc/README.txt
+++ b/doc/README.txt
@@ -230,15 +230,11 @@ Platform notes:
 
 All X86: We quietly assume 486 or better.
 
-Windows:
-Currently AO_REQUIRE_CAS is not supported.
-
 Microsoft compilers:
 Define AO_ASSUME_WINDOWS98 to get access to hardware compare-and-swap
 functionality.  This relies on the InterlockedCompareExchange() function
 which was apparently not supported in Windows95.  (There may be a better
-way to get access to this.)  Currently only X86(32 bit) is supported for
-Windows.
+way to get access to this.)
 
 Gcc on x86:
 Define AO_USE_PENTIUM4_INSTRS to use the Pentium 4 mfence instruction.
diff --git a/src/atomic_ops/generalize.h b/src/atomic_ops/generalize.h
index 8d09336..45950c7 100644
--- a/src/atomic_ops/generalize.h
+++ b/src/atomic_ops/generalize.h
@@ -149,7 +149,7 @@
 
 #if defined(AO_HAVE_test_and_set_full) && !defined(AO_HAVE_nop_full)
    AO_INLINE void
-   AO_nop_full()
+   AO_nop_full(void)
    {
      AO_TS_t dummy = AO_TS_INITIALIZER;
      AO_test_and_set_full(&dummy);
diff --git a/src/atomic_ops/sysdeps/armcc/arm_v6.h b/src/atomic_ops/sysdeps/armcc/arm_v6.h
index 469b994..86376eb 100644
--- a/src/atomic_ops/sysdeps/armcc/arm_v6.h
+++ b/src/atomic_ops/sysdeps/armcc/arm_v6.h
@@ -41,7 +41,7 @@ Dont use with ARM instruction sets lower than v6
 */
 
 AO_INLINE void
-AO_nop_full()
+AO_nop_full(void)
 {
 #ifndef AO_UNIPROCESSOR
 	unsigned int dest=0;
diff --git a/src/atomic_ops/sysdeps/gcc/alpha.h b/src/atomic_ops/sysdeps/gcc/alpha.h
index 90c060c..4e26d47 100644
--- a/src/atomic_ops/sysdeps/gcc/alpha.h
+++ b/src/atomic_ops/sysdeps/gcc/alpha.h
@@ -23,7 +23,7 @@
 	/* Data dependence does not imply read ordering.	*/
 
 AO_INLINE void
-AO_nop_full()
+AO_nop_full(void)
 {
   __asm__ __volatile__("mb" : : : "memory");
 }
@@ -31,7 +31,7 @@ AO_nop_full()
 #define AO_HAVE_nop_full
 
 AO_INLINE void
-AO_nop_write()
+AO_nop_write(void)
 {
   __asm__ __volatile__("wmb" : : : "memory");
 }
diff --git a/src/atomic_ops/sysdeps/gcc/arm.h b/src/atomic_ops/sysdeps/gcc/arm.h
index b9d5d9e..8a9826b 100644
--- a/src/atomic_ops/sysdeps/gcc/arm.h
+++ b/src/atomic_ops/sysdeps/gcc/arm.h
@@ -38,7 +38,7 @@
 #include "../standard_ao_double_t.h"
 
 AO_INLINE void
-AO_nop_full()
+AO_nop_full(void)
 {
 #ifndef AO_UNIPROCESSOR
 	/* issue an data memory barrier (keeps ordering of memory transactions 	*/
diff --git a/src/atomic_ops/sysdeps/gcc/ia64.h b/src/atomic_ops/sysdeps/gcc/ia64.h
index 119b9ed..bd93f70 100644
--- a/src/atomic_ops/sysdeps/gcc/ia64.h
+++ b/src/atomic_ops/sysdeps/gcc/ia64.h
@@ -55,7 +55,7 @@
 #endif
 
 AO_INLINE void
-AO_nop_full()
+AO_nop_full(void)
 {
   __asm__ __volatile__("mf" : : : "memory");
 }
diff --git a/src/atomic_ops/sysdeps/gcc/mips.h b/src/atomic_ops/sysdeps/gcc/mips.h
index 45031f1..c6fd2c1 100644
--- a/src/atomic_ops/sysdeps/gcc/mips.h
+++ b/src/atomic_ops/sysdeps/gcc/mips.h
@@ -27,7 +27,7 @@
 #define AO_NO_DD_ORDERING

 

 AO_INLINE void

-AO_nop_full()

+AO_nop_full(void)

 {

   __asm__ __volatile__(

       "       .set push           \n"

diff --git a/src/atomic_ops/sysdeps/gcc/powerpc.h b/src/atomic_ops/sysdeps/gcc/powerpc.h
index 28d8986..49ab63c 100644
--- a/src/atomic_ops/sysdeps/gcc/powerpc.h
+++ b/src/atomic_ops/sysdeps/gcc/powerpc.h
@@ -37,7 +37,7 @@
 	/* may really be what we want, at least in the 32-bit case.	*/
 
 AO_INLINE void
-AO_nop_full()
+AO_nop_full(void)
 {
   __asm__ __volatile__("sync" : : : "memory");
 }
@@ -46,7 +46,7 @@ AO_nop_full()
 
 /* lwsync apparently works for everything but a StoreLoad barrier.	*/
 AO_INLINE void
-AO_lwsync()
+AO_lwsync(void)
 {
 #ifdef __NO_LWSYNC__
   __asm__ __volatile__("sync" : : : "memory");
diff --git a/src/atomic_ops/sysdeps/gcc/x86.h b/src/atomic_ops/sysdeps/gcc/x86.h
index 662df3f..488cd20 100644
--- a/src/atomic_ops/sysdeps/gcc/x86.h
+++ b/src/atomic_ops/sysdeps/gcc/x86.h
@@ -38,7 +38,7 @@
 
 #if defined(AO_USE_PENTIUM4_INSTRS)
 AO_INLINE void
-AO_nop_full()
+AO_nop_full(void)
 {
   __asm__ __volatile__("mfence" : : : "memory");
 }
diff --git a/src/atomic_ops/sysdeps/generic_pthread.h b/src/atomic_ops/sysdeps/generic_pthread.h
index 519dbf8..b38367f 100644
--- a/src/atomic_ops/sysdeps/generic_pthread.h
+++ b/src/atomic_ops/sysdeps/generic_pthread.h
@@ -38,7 +38,7 @@
 extern pthread_mutex_t AO_pt_lock;
 
 AO_INLINE void
-AO_nop_full()
+AO_nop_full(void)
 {
   pthread_mutex_lock(&AO_pt_lock);
   pthread_mutex_unlock(&AO_pt_lock);
diff --git a/src/atomic_ops/sysdeps/hpc/ia64.h b/src/atomic_ops/sysdeps/hpc/ia64.h
index a7a5071..3fbcc4d 100644
--- a/src/atomic_ops/sysdeps/hpc/ia64.h
+++ b/src/atomic_ops/sysdeps/hpc/ia64.h
@@ -43,7 +43,7 @@
 #endif
 
 AO_INLINE void
-AO_nop_full()
+AO_nop_full(void)
 {
   _Asm_mf();
 }
diff --git a/src/atomic_ops/sysdeps/icc/ia64.h b/src/atomic_ops/sysdeps/icc/ia64.h
index 7eebe27..0278f8b 100644
--- a/src/atomic_ops/sysdeps/icc/ia64.h
+++ b/src/atomic_ops/sysdeps/icc/ia64.h
@@ -98,7 +98,7 @@ AO_int_store_release(volatile unsigned int *p, unsigned int val)
 #define AO_HAVE_int_store_release
 
 AO_INLINE void
-AO_nop_full()
+AO_nop_full(void)
 {
   __mf();
 }
diff --git a/src/atomic_ops/sysdeps/ordered.h b/src/atomic_ops/sysdeps/ordered.h
index 2bcd8d8..cdd2d8e 100644
--- a/src/atomic_ops/sysdeps/ordered.h
+++ b/src/atomic_ops/sysdeps/ordered.h
@@ -28,7 +28,7 @@
 #include "ordered_except_wr.h"
 
 AO_INLINE void
-AO_nop_full()
+AO_nop_full(void)
 {
   AO_compiler_barrier();
 }
diff --git a/src/atomic_ops/sysdeps/ordered_except_wr.h b/src/atomic_ops/sysdeps/ordered_except_wr.h
index 4f29303..3e700b1 100644
--- a/src/atomic_ops/sysdeps/ordered_except_wr.h
+++ b/src/atomic_ops/sysdeps/ordered_except_wr.h
@@ -30,7 +30,7 @@
 #include "read_ordered.h"
 
 AO_INLINE void
-AO_nop_write()
+AO_nop_write(void)
 {
   AO_compiler_barrier();
   /* sfence according to Intel docs.  Pentium 3 and up.	*/
diff --git a/src/atomic_ops/sysdeps/read_ordered.h b/src/atomic_ops/sysdeps/read_ordered.h
index ddf0988..922f5ea 100644
--- a/src/atomic_ops/sysdeps/read_ordered.h
+++ b/src/atomic_ops/sysdeps/read_ordered.h
@@ -28,7 +28,7 @@
  */
 
 AO_INLINE void
-AO_nop_read()
+AO_nop_read(void)
 {
   AO_compiler_barrier();
 }
diff --git a/src/atomic_ops/sysdeps/test_and_set_t_is_ao_t.h b/src/atomic_ops/sysdeps/test_and_set_t_is_ao_t.h
index 663bccf..53c2c5c 100644
--- a/src/atomic_ops/sysdeps/test_and_set_t_is_ao_t.h
+++ b/src/atomic_ops/sysdeps/test_and_set_t_is_ao_t.h
@@ -23,7 +23,7 @@
 /*
  * These are common definitions for architectures on which test_and_set
  * operates on pointer-sized quantities, the "clear" value contains
- * all zeroes, and the "set" value contains all ones.
+ * all zeroes, and the "set" value contains only one lowest bit set.
  * This can be used if test_and_set is synthesized from compare_and_swap.
  */
 typedef enum {AO_TS_clear = 0, AO_TS_set = 1} AO_TS_val;