Fix typos in arm_v6.h, ia64.h, acquire_release_volatile.template

* src/atomic_ops/sysdeps/armcc/arm_v6.h [!AO_UNIPROCESSOR]
(AO_nop_full): Fix typo ("a data memory barrier") in comment.
* src/atomic_ops/sysdeps/icc/ia64.h (AO_char_load_acquire): Fix typo
("a ld.acq instruction") in comment.
* src/atomic_ops/sysdeps/loadstore/acquire_release_volatile.template
(AO_XSIZE_load_acquire): Likewise.
* src/atomic_ops/sysdeps/icc/ia64.h (AO_short_load_acquire,
AO_int_load_acquire): Remove comment duplicating that in
AO_char_load_acquire.
* src/atomic_ops/sysdeps/loadstore/acquire_release_volatile.template
(AO_XSIZE_store_release): Fix typo ("a st.rel instruction") in comment.
* src/atomic_ops/sysdeps/loadstore/acquire_release_volatile.h:
Regenerate.
* src/atomic_ops/sysdeps/loadstore/char_acquire_release_volatile.h:
Likewise.
* src/atomic_ops/sysdeps/loadstore/int_acquire_release_volatile.h:
Likewise.
* src/atomic_ops/sysdeps/loadstore/short_acquire_release_volatile.h:
Likewise.

7 files changed, 13 insertions, 15 deletions

diff --git a/src/atomic_ops/sysdeps/armcc/arm_v6.h b/src/atomic_ops/sysdeps/armcc/arm_v6.h
index c205deb..8508bc7 100644
--- a/src/atomic_ops/sysdeps/armcc/arm_v6.h
+++ b/src/atomic_ops/sysdeps/armcc/arm_v6.h
@@ -50,8 +50,8 @@ AO_nop_full(void)
 {
 # ifndef AO_UNIPROCESSOR
     unsigned int dest=0;
-    /* issue an data memory barrier (keeps ordering of memory transactions */
-    /* before and after this operation)                                    */
+    /* Issue a data memory barrier (keeps ordering of memory transactions  */
+    /* before and after this operation).                                   */
     __asm {
             mcr p15,0,dest,c7,c10,5
             };
diff --git a/src/atomic_ops/sysdeps/icc/ia64.h b/src/atomic_ops/sysdeps/icc/ia64.h
index 6654209..328f9b4 100644
--- a/src/atomic_ops/sysdeps/icc/ia64.h
+++ b/src/atomic_ops/sysdeps/icc/ia64.h
@@ -55,7 +55,7 @@ AO_store_release(volatile AO_t *p, AO_t val)
 AO_INLINE unsigned char
 AO_char_load_acquire(const volatile unsigned char *p)
 {
-  /* A normal volatile load generates an ld.acq         */
+  /* A normal volatile load generates a ld.acq instruction.     */
   return (__ld1_acq((AO_INTEL_PTR_t)p));
 }
 #define AO_HAVE_char_load_acquire
@@ -70,7 +70,6 @@ AO_char_store_release(volatile unsigned char *p, unsigned char val)
 AO_INLINE unsigned short
 AO_short_load_acquire(const volatile unsigned short *p)
 {
-  /* A normal volatile load generates an ld.acq         */
   return (__ld2_acq((AO_INTEL_PTR_t)p));
 }
 #define AO_HAVE_short_load_acquire
@@ -85,7 +84,6 @@ AO_short_store_release(volatile unsigned short *p, unsigned short val)
 AO_INLINE unsigned int
 AO_int_load_acquire(const volatile unsigned int *p)
 {
-  /* A normal volatile load generates an ld.acq         */
   return (__ld4_acq((AO_INTEL_PTR_t)p));
 }
 #define AO_HAVE_int_load_acquire
diff --git a/src/atomic_ops/sysdeps/loadstore/acquire_release_volatile.h b/src/atomic_ops/sysdeps/loadstore/acquire_release_volatile.h
index 51c8560..3c7341e 100644
--- a/src/atomic_ops/sysdeps/loadstore/acquire_release_volatile.h
+++ b/src/atomic_ops/sysdeps/loadstore/acquire_release_volatile.h
@@ -45,7 +45,7 @@ AO_load_acquire(const volatile AO_t *addr)
 {
   AO_t result = *addr;
 
-  /* A normal volatile load generates an ld.acq (on IA-64).     */
+  /* A normal volatile load generates a ld.acq instruction (on IA-64).  */
   AO_GCC_BARRIER();
   return result;
 }
@@ -55,7 +55,7 @@ AO_INLINE void
 AO_store_release(volatile AO_t *addr, AO_t new_val)
 {
   AO_GCC_BARRIER();
-  /* A normal volatile store generates an st.rel (on IA-64).    */
+  /* A normal volatile store generates a st.rel instruction (on IA-64). */
   *addr = new_val;
 }
 #define AO_HAVE_store_release
diff --git a/src/atomic_ops/sysdeps/loadstore/acquire_release_volatile.template b/src/atomic_ops/sysdeps/loadstore/acquire_release_volatile.template
index 10f45a9..a7dfd15 100644
--- a/src/atomic_ops/sysdeps/loadstore/acquire_release_volatile.template
+++ b/src/atomic_ops/sysdeps/loadstore/acquire_release_volatile.template
@@ -45,7 +45,7 @@ AO_XSIZE_load_acquire(const volatile XCTYPE *addr)
 {
   XCTYPE result = *addr;
 
-  /* A normal volatile load generates an ld.acq (on IA-64).     */
+  /* A normal volatile load generates a ld.acq instruction (on IA-64).  */
   AO_GCC_BARRIER();
   return result;
 }
@@ -55,7 +55,7 @@ AO_INLINE void
 AO_XSIZE_store_release(volatile XCTYPE *addr, XCTYPE new_val)
 {
   AO_GCC_BARRIER();
-  /* A normal volatile store generates an st.rel (on IA-64).    */
+  /* A normal volatile store generates a st.rel instruction (on IA-64). */
   *addr = new_val;
 }
 #define AO_HAVE_XSIZE_store_release
diff --git a/src/atomic_ops/sysdeps/loadstore/char_acquire_release_volatile.h b/src/atomic_ops/sysdeps/loadstore/char_acquire_release_volatile.h
index 6de6b8a..1a23058 100644
--- a/src/atomic_ops/sysdeps/loadstore/char_acquire_release_volatile.h
+++ b/src/atomic_ops/sysdeps/loadstore/char_acquire_release_volatile.h
@@ -45,7 +45,7 @@ AO_char_load_acquire(const volatile unsigned/**/char *addr)
 {
   unsigned/**/char result = *addr;
 
-  /* A normal volatile load generates an ld.acq (on IA-64).     */
+  /* A normal volatile load generates a ld.acq instruction (on IA-64).  */
   AO_GCC_BARRIER();
   return result;
 }
@@ -55,7 +55,7 @@ AO_INLINE void
 AO_char_store_release(volatile unsigned/**/char *addr, unsigned/**/char new_val)
 {
   AO_GCC_BARRIER();
-  /* A normal volatile store generates an st.rel (on IA-64).    */
+  /* A normal volatile store generates a st.rel instruction (on IA-64). */
   *addr = new_val;
 }
 #define AO_HAVE_char_store_release
diff --git a/src/atomic_ops/sysdeps/loadstore/int_acquire_release_volatile.h b/src/atomic_ops/sysdeps/loadstore/int_acquire_release_volatile.h
index 6b4875d..18a7e4b 100644
--- a/src/atomic_ops/sysdeps/loadstore/int_acquire_release_volatile.h
+++ b/src/atomic_ops/sysdeps/loadstore/int_acquire_release_volatile.h
@@ -45,7 +45,7 @@ AO_int_load_acquire(const volatile unsigned *addr)
 {
   unsigned result = *addr;
 
-  /* A normal volatile load generates an ld.acq (on IA-64).     */
+  /* A normal volatile load generates a ld.acq instruction (on IA-64).  */
   AO_GCC_BARRIER();
   return result;
 }
@@ -55,7 +55,7 @@ AO_INLINE void
 AO_int_store_release(volatile unsigned *addr, unsigned new_val)
 {
   AO_GCC_BARRIER();
-  /* A normal volatile store generates an st.rel (on IA-64).    */
+  /* A normal volatile store generates a st.rel instruction (on IA-64). */
   *addr = new_val;
 }
 #define AO_HAVE_int_store_release
diff --git a/src/atomic_ops/sysdeps/loadstore/short_acquire_release_volatile.h b/src/atomic_ops/sysdeps/loadstore/short_acquire_release_volatile.h
index e753133..19f7781 100644
--- a/src/atomic_ops/sysdeps/loadstore/short_acquire_release_volatile.h
+++ b/src/atomic_ops/sysdeps/loadstore/short_acquire_release_volatile.h
@@ -45,7 +45,7 @@ AO_short_load_acquire(const volatile unsigned/**/short *addr)
 {
   unsigned/**/short result = *addr;
 
-  /* A normal volatile load generates an ld.acq (on IA-64).     */
+  /* A normal volatile load generates a ld.acq instruction (on IA-64).  */
   AO_GCC_BARRIER();
   return result;
 }
@@ -55,7 +55,7 @@ AO_INLINE void
 AO_short_store_release(volatile unsigned/**/short *addr, unsigned/**/short new_val)
 {
   AO_GCC_BARRIER();
-  /* A normal volatile store generates an st.rel (on IA-64).    */
+  /* A normal volatile store generates a st.rel instruction (on IA-64). */
   *addr = new_val;
 }
 #define AO_HAVE_short_store_release