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authorIvan Maidanski <ivmai@mail.ru>2016-11-08 08:31:21 +0300
committerIvan Maidanski <ivmai@mail.ru>2016-11-08 08:31:21 +0300
commit98e3fdbbd27fbc8556815dbc8cc15579c6874dbd (patch)
tree111e0eb94ac59153b642dc9e32b9f139b4d3d01c
parentc25a7aa4173d724a8264b0b7aa86071c156a0caf (diff)
downloadlibatomic_ops-98e3fdbbd27fbc8556815dbc8cc15579c6874dbd.tar.gz
Remove spaces at EOLn in asm code
* src/atomic_ops/sysdeps/gcc/hexagon.h (AO_test_and_set, AO_compare_and_swap, AO_fetch_compare_and_swap): Remove spaces preceding "\n". * src/atomic_ops/sysdeps/gcc/mips.h (AO_nop_full, AO_fetch_and_add, AO_test_and_set, AO_compare_and_swap): Likewise. * src/atomic_ops/sysdeps/gcc/hexagon.h (AO_fetch_and_add, AO_test_and_set, AO_fetch_compare_and_swap): Align comments.
-rw-r--r--src/atomic_ops/sysdeps/gcc/hexagon.h32
-rw-r--r--src/atomic_ops/sysdeps/gcc/mips.h32
2 files changed, 32 insertions, 32 deletions
diff --git a/src/atomic_ops/sysdeps/gcc/hexagon.h b/src/atomic_ops/sysdeps/gcc/hexagon.h
index da7eb4e..93a236b 100644
--- a/src/atomic_ops/sysdeps/gcc/hexagon.h
+++ b/src/atomic_ops/sysdeps/gcc/hexagon.h
@@ -35,10 +35,10 @@ AO_fetch_and_add(volatile AO_t *addr, AO_t incr)
AO_t newval;
__asm__ __volatile__(
"1:\n"
- " %0 = memw_locked(%3);\n" /* load and reserve */
- " %1 = add (%0,%4);\n" /* increment */
- " memw_locked(%3,p1) = %1;\n" /* store conditional */
- " if (!p1) jump 1b;\n" /* retry if lost reservation */
+ " %0 = memw_locked(%3);\n" /* load and reserve */
+ " %1 = add (%0,%4);\n" /* increment */
+ " memw_locked(%3,p1) = %1;\n" /* store conditional */
+ " if (!p1) jump 1b;\n" /* retry if lost reservation */
: "=&r"(oldval), "=&r"(newval), "+m"(*addr)
: "r"(addr), "r"(incr)
: "memory", "p1");
@@ -54,14 +54,14 @@ AO_test_and_set(volatile AO_TS_t *addr)
__asm__ __volatile__(
"1:\n"
- " %0 = memw_locked(%2);\n" /* load and reserve */
+ " %0 = memw_locked(%2);\n" /* load and reserve */
" {\n"
- " p2 = cmp.eq(%0,#0);\n" /* if load is not zero, */
- " if (!p2.new) jump:nt 2f; \n" /* we are done */
+ " p2 = cmp.eq(%0,#0);\n" /* if load is not zero, */
+ " if (!p2.new) jump:nt 2f;\n" /* we are done */
" }\n"
- " memw_locked(%2,p1) = %3;\n" /* else store conditional */
- " if (!p1) jump 1b;\n" /* retry if lost reservation */
- "2:\n" /* oldval is zero if we set */
+ " memw_locked(%2,p1) = %3;\n" /* else store conditional */
+ " if (!p1) jump 1b;\n" /* retry if lost reservation */
+ "2:\n" /* oldval is zero if we set */
: "=&r"(oldval), "+m"(*addr)
: "r"(addr), "r"(locked_value)
: "memory", "p1", "p2");
@@ -81,7 +81,7 @@ AO_test_and_set(volatile AO_TS_t *addr)
" %0 = memw_locked(%3);\n" /* load and reserve */
" {\n"
" p2 = cmp.eq(%0,%4);\n" /* if load is not equal to */
- " if (!p2.new) jump:nt 2f; \n" /* old, fail */
+ " if (!p2.new) jump:nt 2f;\n" /* old, fail */
" }\n"
" memw_locked(%3,p1) = %5;\n" /* else store conditional */
" if (!p1) jump 1b;\n" /* retry if lost reservation */
@@ -103,13 +103,13 @@ AO_fetch_compare_and_swap(volatile AO_t *addr, AO_t old_val, AO_t new_val)
__asm__ __volatile__(
"1:\n"
- " %0 = memw_locked(%2);\n" /* load and reserve */
+ " %0 = memw_locked(%2);\n" /* load and reserve */
" {\n"
- " p2 = cmp.eq(%0,%3);\n" /* if load is not equal to */
- " if (!p2.new) jump:nt 2f; \n" /* old_val, fail */
+ " p2 = cmp.eq(%0,%3);\n" /* if load is not equal to */
+ " if (!p2.new) jump:nt 2f;\n" /* old_val, fail */
" }\n"
- " memw_locked(%2,p1) = %4;\n" /* else store conditional */
- " if (!p1) jump 1b;\n" /* retry if lost reservation */
+ " memw_locked(%2,p1) = %4;\n" /* else store conditional */
+ " if (!p1) jump 1b;\n" /* retry if lost reservation */
"2:\n"
: "=&r" (__oldval), "+m"(*addr)
: "r" (addr), "r" (old_val), "r" (new_val)
diff --git a/src/atomic_ops/sysdeps/gcc/mips.h b/src/atomic_ops/sysdeps/gcc/mips.h
index f8f154f..e093897 100644
--- a/src/atomic_ops/sysdeps/gcc/mips.h
+++ b/src/atomic_ops/sysdeps/gcc/mips.h
@@ -65,12 +65,12 @@ AO_INLINE void
AO_nop_full(void)
{
__asm__ __volatile__(
- " .set push \n"
+ " .set push\n"
AO_MIPS_SET_ISA
- " .set noreorder \n"
- " .set nomacro \n"
- " sync \n"
- " .set pop "
+ " .set noreorder\n"
+ " .set nomacro\n"
+ " sync\n"
+ " .set pop"
: : : "memory");
}
#define AO_HAVE_nop_full
@@ -93,7 +93,7 @@ AO_fetch_and_add(volatile AO_t *addr, AO_t incr)
AO_MIPS_SC("%1, %2")
" beqz %1, 1b\n"
" nop\n"
- " .set pop "
+ " .set pop"
: "=&r" (result), "=&r" (temp), "+m" (*addr)
: "Ir" (incr)
: "memory");
@@ -118,7 +118,7 @@ AO_test_and_set(volatile AO_TS_t *addr)
AO_MIPS_SC("%1, %2")
" beqz %1, 1b\n"
" nop\n"
- " .set pop "
+ " .set pop"
: "=&r" (oldval), "=&r" (temp), "+m" (*addr)
: "r" (1)
: "memory");
@@ -137,19 +137,19 @@ AO_test_and_set(volatile AO_TS_t *addr)
register int temp;
__asm__ __volatile__(
- " .set push \n"
+ " .set push\n"
AO_MIPS_SET_ISA
- " .set noreorder \n"
- " .set nomacro \n"
+ " .set noreorder\n"
+ " .set nomacro\n"
"1: "
AO_MIPS_LL("%0, %1")
- " bne %0, %4, 2f \n"
- " move %0, %3 \n"
+ " bne %0, %4, 2f\n"
+ " move %0, %3\n"
AO_MIPS_SC("%0, %1")
- " .set pop \n"
- " beqz %0, 1b \n"
- " li %2, 1 \n"
- "2: "
+ " .set pop\n"
+ " beqz %0, 1b\n"
+ " li %2, 1\n"
+ "2:"
: "=&r" (temp), "+m" (*addr), "+r" (was_equal)
: "r" (new_val), "r" (old)
: "memory");