From 3840d49aaa831d649b1597518a2903dfed0d57f3 Mon Sep 17 00:00:00 2001
From: Stef O'Rear <sorear2@gmail.com>
Date: Sun, 11 Mar 2018 05:55:15 -0700
Subject: New RISC-V port (#281)

* Add RISC-V support

This patch adds support for the RISC-V architecture (https://riscv.org).

This patch has been tested using QEMU user-mode emulation and GCC 7.2.0
in the following configurations:

* -march=rv32imac -mabi=ilp32
* -march=rv32g -mabi=ilp32d
* -march=rv64imac -mabi=lp64
* -march=rv64g -mabi=lp64d

The ABI currently can be found at
https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md .

* Add RISC-V to README

* RISC-V: fix configure.host
---
 configure.host | 5 +++++
 1 file changed, 5 insertions(+)

(limited to 'configure.host')

diff --git a/configure.host b/configure.host
index 34e83f7..7634c3a 100644
--- a/configure.host
+++ b/configure.host
@@ -206,6 +206,11 @@ case "${host}" in
 	TARGET=POWERPC; TARGETDIR=powerpc
 	;;
 
+  riscv*-*)
+	TARGET=RISCV; TARGETDIR=riscv
+	SOURCES="ffi.c sysv.S"
+	;;
+
   s390-*-* | s390x-*-*)
 	TARGET=S390; TARGETDIR=s390
 	SOURCES="ffi.c sysv.S"
-- 
cgit v1.2.1