diff options
| author | Andreas Schwab <schwab@suse.de> | 2020-01-07 14:51:19 +0100 |
|---|---|---|
| committer | Paul Moore <paul@paul-moore.com> | 2020-02-23 10:27:58 -0500 |
| commit | 5432e15521d5ce5a7d3f26bf78674cbaa9d73d1f (patch) | |
| tree | f0bf4ab2fcb55620c15aae9f4c6169bea6d73285 /tests | |
| parent | 0a4c0300ebcc982cf419a4f7382ffc28e4792d2a (diff) | |
| download | libseccomp-5432e15521d5ce5a7d3f26bf78674cbaa9d73d1f.tar.gz | |
arch: Add RISC-V 64-bit support
Signed-off-by: Andreas Schwab <schwab@suse.de>
[PM: minor macro shuffling in seccomp.h.in]
Signed-off-by: Paul Moore <paul@paul-moore.com>
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/15-basic-resolver.c | 1 | ||||
| -rw-r--r-- | tests/16-sim-arch_basic.c | 6 | ||||
| -rwxr-xr-x | tests/16-sim-arch_basic.py | 1 | ||||
| -rw-r--r-- | tests/23-sim-arch_all_le_basic.c | 3 | ||||
| -rwxr-xr-x | tests/23-sim-arch_all_le_basic.py | 1 | ||||
| -rwxr-xr-x | tests/regression | 6 |
6 files changed, 16 insertions, 2 deletions
diff --git a/tests/15-basic-resolver.c b/tests/15-basic-resolver.c index 0c1eefe..2679270 100644 --- a/tests/15-basic-resolver.c +++ b/tests/15-basic-resolver.c @@ -45,6 +45,7 @@ unsigned int arch_list[] = { SCMP_ARCH_S390X, SCMP_ARCH_PARISC, SCMP_ARCH_PARISC64, + SCMP_ARCH_RISCV64, -1 }; diff --git a/tests/16-sim-arch_basic.c b/tests/16-sim-arch_basic.c index 5413e18..0b141e1 100644 --- a/tests/16-sim-arch_basic.c +++ b/tests/16-sim-arch_basic.c @@ -92,6 +92,9 @@ int main(int argc, char *argv[]) rc = seccomp_arch_add(ctx, SCMP_ARCH_PPC64LE); if (rc != 0) goto out; + rc = seccomp_arch_add(ctx, SCMP_ARCH_RISCV64); + if (rc != 0) + goto out; rc = seccomp_rule_add(ctx, SCMP_ACT_ALLOW, SCMP_SYS(read), 1, SCMP_A0(SCMP_CMP_EQ, STDIN_FILENO)); @@ -156,6 +159,9 @@ int main(int argc, char *argv[]) rc = seccomp_arch_remove(ctx, SCMP_ARCH_PPC64LE); if (rc != 0) goto out; + rc = seccomp_arch_remove(ctx, SCMP_ARCH_RISCV64); + if (rc != 0) + goto out; out: seccomp_release(ctx); diff --git a/tests/16-sim-arch_basic.py b/tests/16-sim-arch_basic.py index 7d7a05f..846553f 100755 --- a/tests/16-sim-arch_basic.py +++ b/tests/16-sim-arch_basic.py @@ -44,6 +44,7 @@ def test(args): f.add_arch(Arch("mipsel64")) f.add_arch(Arch("mipsel64n32")) f.add_arch(Arch("ppc64le")) + f.add_arch(Arch("riscv64")) f.add_rule(ALLOW, "read", Arg(0, EQ, sys.stdin.fileno())) f.add_rule(ALLOW, "write", Arg(0, EQ, sys.stdout.fileno())) f.add_rule(ALLOW, "write", Arg(0, EQ, sys.stderr.fileno())) diff --git a/tests/23-sim-arch_all_le_basic.c b/tests/23-sim-arch_all_le_basic.c index 5672980..32739e5 100644 --- a/tests/23-sim-arch_all_le_basic.c +++ b/tests/23-sim-arch_all_le_basic.c @@ -71,6 +71,9 @@ int main(int argc, char *argv[]) rc = seccomp_arch_add(ctx, seccomp_arch_resolve_name("ppc64le")); if (rc != 0) goto out; + rc = seccomp_arch_add(ctx, seccomp_arch_resolve_name("riscv64")); + if (rc != 0) + goto out; rc = seccomp_rule_add(ctx, SCMP_ACT_ALLOW, SCMP_SYS(read), 1, SCMP_A0(SCMP_CMP_EQ, STDIN_FILENO)); diff --git a/tests/23-sim-arch_all_le_basic.py b/tests/23-sim-arch_all_le_basic.py index 5927f37..33eedb1 100755 --- a/tests/23-sim-arch_all_le_basic.py +++ b/tests/23-sim-arch_all_le_basic.py @@ -40,6 +40,7 @@ def test(args): f.add_arch(Arch("mipsel64")) f.add_arch(Arch("mipsel64n32")) f.add_arch(Arch("ppc64le")) + f.add_arch(Arch("riscv64")) f.add_rule(ALLOW, "read", Arg(0, EQ, sys.stdin.fileno())) f.add_rule(ALLOW, "write", Arg(0, EQ, sys.stdout.fileno())) f.add_rule(ALLOW, "write", Arg(0, EQ, sys.stderr.fileno())) diff --git a/tests/regression b/tests/regression index 56822fb..ef98c3d 100755 --- a/tests/regression +++ b/tests/regression @@ -25,7 +25,8 @@ GLBL_ARCH_LE_SUPPORT=" \ x86 x86_64 x32 \ arm aarch64 \ mipsel mipsel64 mipsel64n32 \ - ppc64le" + ppc64le \ + riscv64" GLBL_ARCH_BE_SUPPORT=" \ mips mips64 mips64n32 \ parisc parisc64 \ @@ -46,6 +47,7 @@ GLBL_ARCH_64B_SUPPORT=" \ mips64 \ parisc64 \ ppc64 \ + riscv64 \ s390x" GLBL_SYS_ARCH="../tools/scmp_arch_detect" @@ -777,7 +779,7 @@ function run_test_live() { # setup the arch specific return values case "$arch" in - x86|x86_64|x32|arm|aarch64|parisc|parisc64|ppc|ppc64|ppc64le|ppc|s390|s390x) + x86|x86_64|x32|arm|aarch64|parisc|parisc64|ppc|ppc64|ppc64le|ppc|s390|s390x|riscv64) rc_kill_process=159 rc_kill=159 rc_allow=160 |