render: clear background using 3D pipeline on GEN8+

Remove the extra sync between BCS and CS rings

Signed-off-by: Haihao Xiang <haihao.xiang@intel.com>

10 files changed, 389 insertions, 130 deletions

diff --git a/src/gen8_render.c b/src/gen8_render.c
index a3ff1e6e..a89eb483 100644
--- a/src/gen8_render.c
+++ b/src/gen8_render.c
@@ -73,6 +73,10 @@ static const uint32_t ps_subpic_kernel_static_gen8[][4] = {
 #include "shaders/render/exa_wm_write.g8b"
 };
 
+static const uint32_t ps_clear_kernel_static_gen8[][4] = {
+#include "shaders/render/exa_wm_src_affine.g8b"
+#include "shaders/render/exa_wm_clear.g8b"
+};
 
 #define SURFACE_STATE_PADDED_SIZE       SURFACE_STATE_PADDED_SIZE_GEN8
 
@@ -82,7 +86,8 @@ static const uint32_t ps_subpic_kernel_static_gen8[][4] = {
 enum {
     SF_KERNEL = 0,
     PS_KERNEL,
-    PS_SUBPIC_KERNEL
+    PS_SUBPIC_KERNEL,
+    PS_CLEAR_KERNEL
 };
 
 static struct i965_kernel render_kernels_gen8[] = {
@@ -107,6 +112,14 @@ static struct i965_kernel render_kernels_gen8[] = {
         ps_subpic_kernel_static_gen8,
         sizeof(ps_subpic_kernel_static_gen8),
         NULL
+    },
+
+    {
+        "PS_CLEAR",
+        PS_CLEAR_KERNEL,
+        ps_clear_kernel_static_gen8,
+        sizeof(ps_clear_kernel_static_gen8),
+        NULL
     }
 };
 
@@ -347,7 +360,8 @@ static void
 i965_fill_vertex_buffer(
     VADriverContextP ctx,
     float tex_coords[4], /* [(u1,v1);(u2,v2)] */
-    float vid_coords[4]  /* [(x1,y1);(x2,y2)] */
+    float vid_coords[4], /* [(x1,y1);(x2,y2)] */
+    int offset
 )
 {
     struct i965_driver_data * const i965 = i965_driver_data(ctx);
@@ -380,7 +394,7 @@ i965_fill_vertex_buffer(
     vb[10] = vid_coords[X1];
     vb[11] = vid_coords[Y1];
 
-    dri_bo_subdata(i965->render_state.vb.vertex_buffer, 0, sizeof(vb), vb);
+    dri_bo_subdata(i965->render_state.vb.vertex_buffer, offset, sizeof(vb), vb);
 }
 
 static void
@@ -414,7 +428,7 @@ i965_subpic_render_upload_vertex(VADriverContextP ctx,
     vid_coords[2] = (float)(dst_rect.x + dst_rect.width);
     vid_coords[3] = (float)(dst_rect.y + dst_rect.height);
 
-    i965_fill_vertex_buffer(ctx, tex_coords, vid_coords);
+    i965_fill_vertex_buffer(ctx, tex_coords, vid_coords, 0);
 }
 
 static void
@@ -444,7 +458,24 @@ i965_render_upload_vertex(
     vid_coords[2] = vid_coords[0] + dst_rect->width;
     vid_coords[3] = vid_coords[1] + dst_rect->height;
 
-    i965_fill_vertex_buffer(ctx, tex_coords, vid_coords);
+    i965_fill_vertex_buffer(ctx, tex_coords, vid_coords, 0);
+
+    /*
+     * The vertices below are for background, and always set tex-coordinates
+     * although the tex-coordinates are not used in the the corresponding PS
+     * kernel.
+     */
+    tex_coords[0] = 0.0F;
+    tex_coords[1] = 0.0F;
+    tex_coords[2] = 1.0F;
+    tex_coords[3] = 1.0F;
+
+    vid_coords[0] = dest_region->x;
+    vid_coords[1] = dest_region->y;
+    vid_coords[2] = vid_coords[0] + dest_region->width;
+    vid_coords[3] = vid_coords[1] + dest_region->height;
+
+    i965_fill_vertex_buffer(ctx, tex_coords, vid_coords, 12 * sizeof(float));
 }
 
 static void
@@ -491,53 +522,6 @@ i965_render_upload_image_palette(
     ADVANCE_BATCH(batch);
 }
 
-static void
-gen8_clear_dest_region(VADriverContextP ctx)
-{
-    struct i965_driver_data *i965 = i965_driver_data(ctx);
-    struct intel_batchbuffer *batch = i965->batch;
-    struct i965_render_state *render_state = &i965->render_state;
-    struct intel_region *dest_region = render_state->draw_region;
-    unsigned int blt_cmd, br13;
-    int pitch;
-
-    blt_cmd = GEN8_XY_COLOR_BLT_CMD;
-    br13 = 0xf0 << 16;
-    pitch = dest_region->pitch;
-
-    if (dest_region->cpp == 4) {
-        br13 |= BR13_8888;
-        blt_cmd |= (XY_COLOR_BLT_WRITE_RGB | XY_COLOR_BLT_WRITE_ALPHA);
-    } else {
-        assert(dest_region->cpp == 2);
-        br13 |= BR13_565;
-    }
-
-    if (dest_region->tiling != I915_TILING_NONE) {
-        blt_cmd |= XY_COLOR_BLT_DST_TILED;
-        pitch /= 4;
-    }
-
-    br13 |= pitch;
-
-    intel_batchbuffer_start_atomic_blt(batch, 24);
-    BEGIN_BLT_BATCH(batch, 7);
-
-    OUT_BATCH(batch, blt_cmd);
-    OUT_BATCH(batch, br13);
-    OUT_BATCH(batch, (dest_region->y << 16) | (dest_region->x));
-    OUT_BATCH(batch, ((dest_region->y + dest_region->height) << 16) |
-              (dest_region->x + dest_region->width));
-    OUT_RELOC(batch, dest_region->bo,
-              I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
-              0);
-    OUT_BATCH(batch, 0x0);
-    OUT_BATCH(batch, 0x0);
-    ADVANCE_BATCH(batch);
-    intel_batchbuffer_end_atomic(batch);
-}
-
-
 /*
  * for GEN8
  */
@@ -890,7 +874,7 @@ gen8_emit_cc_state_pointers(VADriverContextP ctx)
 }
 
 static void
-gen8_emit_vertices(VADriverContextP ctx)
+gen8_emit_vertices(VADriverContextP ctx, int offset)
 {
     struct i965_driver_data *i965 = i965_driver_data(ctx);
     struct intel_batchbuffer *batch = i965->batch;
@@ -903,7 +887,7 @@ gen8_emit_vertices(VADriverContextP ctx)
               (0 << GEN8_VB0_MOCS_SHIFT) |
               GEN7_VB0_ADDRESS_MODIFYENABLE |
               ((4 * 4) << VB0_BUFFER_PITCH_SHIFT));
-    OUT_RELOC(batch, render_state->vb.vertex_buffer, I915_GEM_DOMAIN_VERTEX, 0, 0);
+    OUT_RELOC(batch, render_state->vb.vertex_buffer, I915_GEM_DOMAIN_VERTEX, 0, offset);
     OUT_BATCH(batch, 0);
     OUT_BATCH(batch, 12 * 4);
     ADVANCE_BATCH(batch);
@@ -1382,7 +1366,8 @@ gen8_emit_wm_state(VADriverContextP ctx, int kernel)
               (GEN8_PSX_PIXEL_SHADER_VALID | GEN8_PSX_ATTRIBUTE_ENABLE));
     ADVANCE_BATCH(batch);
 
-    if (kernel == PS_KERNEL) {
+    if (kernel == PS_KERNEL ||
+        kernel == PS_CLEAR_KERNEL) {
         BEGIN_BATCH(batch, 2);
         OUT_BATCH(batch, GEN8_3DSTATE_PSBLEND | (2 - 2));
         OUT_BATCH(batch,
@@ -1571,7 +1556,39 @@ gen7_emit_drawing_rectangle(VADriverContextP ctx)
 }
 
 static void
-gen8_render_emit_states(VADriverContextP ctx, int kernel)
+gen8_render_emit_states(VADriverContextP ctx)
+{
+    struct i965_driver_data *i965 = i965_driver_data(ctx);
+    struct intel_batchbuffer *batch = i965->batch;
+
+    intel_batchbuffer_start_atomic(batch, 0x1000);
+    intel_batchbuffer_emit_mi_flush(batch);
+    gen8_emit_invarient_states(ctx);
+    gen8_emit_state_base_address(ctx);
+    gen8_emit_viewport_state_pointers(ctx);
+    gen8_emit_urb(ctx);
+    gen8_emit_cc_state_pointers(ctx);
+    gen8_emit_sampler_state_pointers(ctx);
+    gen8_emit_wm_hz_op(ctx);
+    gen8_emit_bypass_state(ctx);
+    gen8_emit_vs_state(ctx);
+    gen8_emit_clip_state(ctx);
+    gen8_emit_sf_state(ctx);
+    gen8_emit_depth_stencil_state(ctx);
+    gen8_emit_depth_buffer_state(ctx);
+    gen7_emit_drawing_rectangle(ctx);
+    gen8_emit_vertex_element_state(ctx);
+    /* clear background */
+    gen8_emit_wm_state(ctx, PS_CLEAR_KERNEL);
+    gen8_emit_vertices(ctx, 12 * sizeof(float));
+    /* draw the image */
+    gen8_emit_wm_state(ctx, PS_KERNEL);
+    gen8_emit_vertices(ctx, 0);
+    intel_batchbuffer_end_atomic(batch);
+}
+
+static void
+gen8_subpicture_render_emit_states(VADriverContextP ctx)
 {
     struct i965_driver_data *i965 = i965_driver_data(ctx);
     struct intel_batchbuffer *batch = i965->batch;
@@ -1590,11 +1607,11 @@ gen8_render_emit_states(VADriverContextP ctx, int kernel)
     gen8_emit_clip_state(ctx);
     gen8_emit_sf_state(ctx);
     gen8_emit_depth_stencil_state(ctx);
-    gen8_emit_wm_state(ctx, kernel);
+    gen8_emit_wm_state(ctx, PS_SUBPIC_KERNEL);
     gen8_emit_depth_buffer_state(ctx);
     gen7_emit_drawing_rectangle(ctx);
     gen8_emit_vertex_element_state(ctx);
-    gen8_emit_vertices(ctx);
+    gen8_emit_vertices(ctx, 0);
     intel_batchbuffer_end_atomic(batch);
 }
 
@@ -1612,8 +1629,7 @@ gen8_render_put_surface(
 
     gen8_render_initialize(ctx);
     gen8_render_setup_states(ctx, obj_surface, src_rect, dst_rect, flags);
-    gen8_clear_dest_region(ctx);
-    gen8_render_emit_states(ctx, PS_KERNEL);
+    gen8_render_emit_states(ctx);
     intel_batchbuffer_flush(batch);
 }
 
@@ -1714,7 +1730,7 @@ gen8_render_put_subpicture(
     assert(obj_subpic);
     gen8_render_initialize(ctx);
     gen8_subpicture_render_setup_states(ctx, obj_surface, src_rect, dst_rect);
-    gen8_render_emit_states(ctx, PS_SUBPIC_KERNEL);
+    gen8_subpicture_render_emit_states(ctx);
     i965_render_upload_image_palette(ctx, obj_subpic->obj_image, 0xff);
     intel_batchbuffer_flush(batch);
 }
diff --git a/src/gen9_render.c b/src/gen9_render.c
index b609fea5..305a11b2 100644
--- a/src/gen9_render.c
+++ b/src/gen9_render.c
@@ -67,6 +67,10 @@ static const uint32_t ps_subpic_kernel_static_gen9[][4] = {
 #include "shaders/render/exa_wm_write.g9b"
 };
 
+static const uint32_t ps_clear_kernel_static_gen9[][4] = {
+#include "shaders/render/exa_wm_src_affine.g9b"
+#include "shaders/render/exa_wm_clear.g9b"
+};
 
 #define SURFACE_STATE_PADDED_SIZE       SURFACE_STATE_PADDED_SIZE_GEN8
 
@@ -76,7 +80,8 @@ static const uint32_t ps_subpic_kernel_static_gen9[][4] = {
 enum {
     SF_KERNEL = 0,
     PS_KERNEL,
-    PS_SUBPIC_KERNEL
+    PS_SUBPIC_KERNEL,
+    PS_CLEAR_KERNEL
 };
 
 static struct i965_kernel render_kernels_gen9[] = {
@@ -101,6 +106,14 @@ static struct i965_kernel render_kernels_gen9[] = {
         ps_subpic_kernel_static_gen9,
         sizeof(ps_subpic_kernel_static_gen9),
         NULL
+    },
+
+    {
+        "PS_CLEAR",
+        PS_CLEAR_KERNEL,
+        ps_clear_kernel_static_gen9,
+        sizeof(ps_clear_kernel_static_gen9),
+        NULL
     }
 };
 
@@ -351,7 +364,8 @@ static void
 i965_fill_vertex_buffer(
     VADriverContextP ctx,
     float tex_coords[4], /* [(u1,v1);(u2,v2)] */
-    float vid_coords[4]  /* [(x1,y1);(x2,y2)] */
+    float vid_coords[4], /* [(x1,y1);(x2,y2)] */
+    int offset
 )
 {
     struct i965_driver_data * const i965 = i965_driver_data(ctx);
@@ -384,7 +398,7 @@ i965_fill_vertex_buffer(
     vb[10] = vid_coords[X1];
     vb[11] = vid_coords[Y1];
 
-    dri_bo_subdata(i965->render_state.vb.vertex_buffer, 0, sizeof(vb), vb);
+    dri_bo_subdata(i965->render_state.vb.vertex_buffer, offset, sizeof(vb), vb);
 }
 
 static void
@@ -418,7 +432,7 @@ i965_subpic_render_upload_vertex(VADriverContextP ctx,
     vid_coords[2] = (float)(dst_rect.x + dst_rect.width);
     vid_coords[3] = (float)(dst_rect.y + dst_rect.height);
 
-    i965_fill_vertex_buffer(ctx, tex_coords, vid_coords);
+    i965_fill_vertex_buffer(ctx, tex_coords, vid_coords, 0);
 }
 
 static void
@@ -448,7 +462,24 @@ i965_render_upload_vertex(
     vid_coords[2] = vid_coords[0] + dst_rect->width;
     vid_coords[3] = vid_coords[1] + dst_rect->height;
 
-    i965_fill_vertex_buffer(ctx, tex_coords, vid_coords);
+    i965_fill_vertex_buffer(ctx, tex_coords, vid_coords, 0);
+
+    /*
+     * The vertices below are for background, and always set tex-coordinates
+     * although the tex-coordinates are not used in the the corresponding PS
+     * kernel.
+     */
+    tex_coords[0] = 0.0F;
+    tex_coords[1] = 0.0F;
+    tex_coords[2] = 1.0F;
+    tex_coords[3] = 1.0F;
+
+    vid_coords[0] = dest_region->x;
+    vid_coords[1] = dest_region->y;
+    vid_coords[2] = vid_coords[0] + dest_region->width;
+    vid_coords[3] = vid_coords[1] + dest_region->height;
+
+    i965_fill_vertex_buffer(ctx, tex_coords, vid_coords, 12 * sizeof(float));
 }
 
 static void
@@ -495,53 +526,6 @@ i965_render_upload_image_palette(
     ADVANCE_BATCH(batch);
 }
 
-static void
-gen9_clear_dest_region(VADriverContextP ctx)
-{
-    struct i965_driver_data *i965 = i965_driver_data(ctx);
-    struct intel_batchbuffer *batch = i965->batch;
-    struct i965_render_state *render_state = &i965->render_state;
-    struct intel_region *dest_region = render_state->draw_region;
-    unsigned int blt_cmd, br13;
-    int pitch;
-
-    blt_cmd = GEN8_XY_COLOR_BLT_CMD;
-    br13 = 0xf0 << 16;
-    pitch = dest_region->pitch;
-
-    if (dest_region->cpp == 4) {
-        br13 |= BR13_8888;
-        blt_cmd |= (XY_COLOR_BLT_WRITE_RGB | XY_COLOR_BLT_WRITE_ALPHA);
-    } else {
-        assert(dest_region->cpp == 2);
-        br13 |= BR13_565;
-    }
-
-    if (dest_region->tiling != I915_TILING_NONE) {
-        blt_cmd |= XY_COLOR_BLT_DST_TILED;
-        pitch /= 4;
-    }
-
-    br13 |= pitch;
-
-    intel_batchbuffer_start_atomic_blt(batch, 24);
-    BEGIN_BLT_BATCH(batch, 7);
-
-    OUT_BATCH(batch, blt_cmd);
-    OUT_BATCH(batch, br13);
-    OUT_BATCH(batch, (dest_region->y << 16) | (dest_region->x));
-    OUT_BATCH(batch, ((dest_region->y + dest_region->height) << 16) |
-              (dest_region->x + dest_region->width));
-    OUT_RELOC(batch, dest_region->bo,
-              I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
-              0);
-    OUT_BATCH(batch, 0x0);
-    OUT_BATCH(batch, 0x0);
-    ADVANCE_BATCH(batch);
-    intel_batchbuffer_end_atomic(batch);
-}
-
-
 /*
  * for GEN8
  */
@@ -900,7 +884,7 @@ gen9_emit_cc_state_pointers(VADriverContextP ctx)
 }
 
 static void
-gen9_emit_vertices(VADriverContextP ctx)
+gen9_emit_vertices(VADriverContextP ctx, int offset)
 {
     struct i965_driver_data *i965 = i965_driver_data(ctx);
     struct intel_batchbuffer *batch = i965->batch;
@@ -913,7 +897,7 @@ gen9_emit_vertices(VADriverContextP ctx)
               (0 << GEN8_VB0_MOCS_SHIFT) |
               GEN7_VB0_ADDRESS_MODIFYENABLE |
               ((4 * 4) << VB0_BUFFER_PITCH_SHIFT));
-    OUT_RELOC(batch, render_state->vb.vertex_buffer, I915_GEM_DOMAIN_VERTEX, 0, 0);
+    OUT_RELOC(batch, render_state->vb.vertex_buffer, I915_GEM_DOMAIN_VERTEX, 0, offset);
     OUT_BATCH(batch, 0);
     OUT_BATCH(batch, 12 * 4);
     ADVANCE_BATCH(batch);
@@ -1405,7 +1389,8 @@ gen9_emit_wm_state(VADriverContextP ctx, int kernel)
               (GEN8_PSX_PIXEL_SHADER_VALID | GEN8_PSX_ATTRIBUTE_ENABLE));
     ADVANCE_BATCH(batch);
 
-    if (kernel == PS_KERNEL) {
+    if (kernel == PS_KERNEL ||
+        kernel == PS_CLEAR_KERNEL) {
         BEGIN_BATCH(batch, 2);
         OUT_BATCH(batch, GEN8_3DSTATE_PSBLEND | (2 - 2));
         OUT_BATCH(batch,
@@ -1594,7 +1579,39 @@ gen9_emit_drawing_rectangle(VADriverContextP ctx)
 }
 
 static void
-gen9_render_emit_states(VADriverContextP ctx, int kernel)
+gen9_render_emit_states(VADriverContextP ctx)
+{
+    struct i965_driver_data *i965 = i965_driver_data(ctx);
+    struct intel_batchbuffer *batch = i965->batch;
+
+    intel_batchbuffer_start_atomic(batch, 0x1000);
+    intel_batchbuffer_emit_mi_flush(batch);
+    gen9_emit_invarient_states(ctx);
+    gen9_emit_state_base_address(ctx);
+    gen9_emit_viewport_state_pointers(ctx);
+    gen9_emit_urb(ctx);
+    gen9_emit_cc_state_pointers(ctx);
+    gen9_emit_sampler_state_pointers(ctx);
+    gen9_emit_wm_hz_op(ctx);
+    gen9_emit_bypass_state(ctx);
+    gen9_emit_vs_state(ctx);
+    gen9_emit_clip_state(ctx);
+    gen9_emit_sf_state(ctx);
+    gen9_emit_depth_stencil_state(ctx);
+    gen9_emit_depth_buffer_state(ctx);
+    gen9_emit_drawing_rectangle(ctx);
+    gen9_emit_vertex_element_state(ctx);
+    /* clear background */
+    gen9_emit_wm_state(ctx, PS_CLEAR_KERNEL);
+    gen9_emit_vertices(ctx, 12 * sizeof(float));
+    /* draw the image */
+    gen9_emit_wm_state(ctx, PS_KERNEL);
+    gen9_emit_vertices(ctx, 0);
+    intel_batchbuffer_end_atomic(batch);
+}
+
+static void
+gen9_subpicture_render_emit_states(VADriverContextP ctx)
 {
     struct i965_driver_data *i965 = i965_driver_data(ctx);
     struct intel_batchbuffer *batch = i965->batch;
@@ -1613,11 +1630,11 @@ gen9_render_emit_states(VADriverContextP ctx, int kernel)
     gen9_emit_clip_state(ctx);
     gen9_emit_sf_state(ctx);
     gen9_emit_depth_stencil_state(ctx);
-    gen9_emit_wm_state(ctx, kernel);
+    gen9_emit_wm_state(ctx, PS_SUBPIC_KERNEL);
     gen9_emit_depth_buffer_state(ctx);
     gen9_emit_drawing_rectangle(ctx);
     gen9_emit_vertex_element_state(ctx);
-    gen9_emit_vertices(ctx);
+    gen9_emit_vertices(ctx, 0);
     intel_batchbuffer_end_atomic(batch);
 }
 
@@ -1635,8 +1652,7 @@ gen9_render_put_surface(
 
     gen9_render_initialize(ctx);
     gen9_render_setup_states(ctx, obj_surface, src_rect, dst_rect, flags);
-    gen9_clear_dest_region(ctx);
-    gen9_render_emit_states(ctx, PS_KERNEL);
+    gen9_render_emit_states(ctx);
     intel_batchbuffer_flush(batch);
 }
 
@@ -1737,7 +1753,7 @@ gen9_render_put_subpicture(
     assert(obj_subpic);
     gen9_render_initialize(ctx);
     gen9_subpicture_render_setup_states(ctx, obj_surface, src_rect, dst_rect);
-    gen9_render_emit_states(ctx, PS_SUBPIC_KERNEL);
+    gen9_subpicture_render_emit_states(ctx);
     i965_render_upload_image_palette(ctx, obj_subpic->obj_image, 0xff);
     intel_batchbuffer_flush(batch);
 }
diff --git a/src/i965_render.c b/src/i965_render.c
index 0f5859a7..cc56e35b 100644
--- a/src/i965_render.c
+++ b/src/i965_render.c
@@ -161,7 +161,8 @@ static uint32_t float_to_uint(float f)
 enum {
     SF_KERNEL = 0,
     PS_KERNEL,
-    PS_SUBPIC_KERNEL
+    PS_SUBPIC_KERNEL,
+    PS_CLEAR_KERNEL
 };
 
 static struct i965_kernel render_kernels_gen4[] = {
@@ -186,6 +187,15 @@ static struct i965_kernel render_kernels_gen4[] = {
         ps_subpic_kernel_static,
         sizeof(ps_subpic_kernel_static),
         NULL
+    },
+
+    // Not used
+    {
+        "PS_CLEAR",
+        PS_CLEAR_KERNEL,
+        NULL,
+        0,
+        0
     }
 };
 
@@ -211,6 +221,15 @@ static struct i965_kernel render_kernels_gen5[] = {
         ps_subpic_kernel_static_gen5,
         sizeof(ps_subpic_kernel_static_gen5),
         NULL
+    },
+
+    // Not used
+    {
+        "PS_CLEAR",
+        PS_CLEAR_KERNEL,
+        NULL,
+        0,
+        0
     }
 };
 
@@ -236,6 +255,15 @@ static struct i965_kernel render_kernels_gen6[] = {
         ps_subpic_kernel_static_gen6,
         sizeof(ps_subpic_kernel_static_gen6),
         NULL
+    },
+
+    // Not used
+    {
+        "PS_CLEAR",
+        PS_CLEAR_KERNEL,
+        NULL,
+        0,
+        0
     }
 };
 
@@ -261,6 +289,15 @@ static struct i965_kernel render_kernels_gen7[] = {
         ps_subpic_kernel_static_gen7,
         sizeof(ps_subpic_kernel_static_gen7),
         NULL
+    },
+
+    // Not used
+    {
+        "PS_CLEAR",
+        PS_CLEAR_KERNEL,
+        NULL,
+        0,
+        0
     }
 };
 
@@ -286,6 +323,15 @@ static struct i965_kernel render_kernels_gen7_haswell[] = {
         ps_subpic_kernel_static_gen7,
         sizeof(ps_subpic_kernel_static_gen7),
         NULL
+    },
+
+    // Not used
+    {
+        "PS_CLEAR",
+        PS_CLEAR_KERNEL,
+        NULL,
+        0,
+        0
     }
 };
 
diff --git a/src/i965_render.h b/src/i965_render.h
index a3739247..fb4619a7 100644
--- a/src/i965_render.h
+++ b/src/i965_render.h
@@ -31,7 +31,7 @@
 #define MAX_SAMPLERS            16
 #define MAX_RENDER_SURFACES     (MAX_SAMPLERS + 1)
 
-#define NUM_RENDER_KERNEL       3
+#define NUM_RENDER_KERNEL       4
 
 #define VA_SRC_COLOR_MASK       0x000000f0
 
@@ -73,7 +73,7 @@ struct i965_render_state {
 
     int pp_flag; /* 0: disable, 1: enable */
 
-    struct i965_kernel render_kernels[3];
+    struct i965_kernel render_kernels[NUM_RENDER_KERNEL];
 
     struct {
         dri_bo *bo;
diff --git a/src/shaders/render/Makefile.am b/src/shaders/render/Makefile.am
index f10e1b36..6d306aef 100644
--- a/src/shaders/render/Makefile.am
+++ b/src/shaders/render/Makefile.am
@@ -60,7 +60,8 @@ INTEL_G6B =				\
 	exa_wm_yuv_rgb.g6b
 
 INTEL_G7I = $(INTEL_G4I)		\
-	exa_wm_write.g7i
+	exa_wm_write.g7i		\
+	exa_wm_clear.g7i
 
 INTEL_G7A =				\
 	exa_wm_src_affine.g7a 		\
@@ -92,7 +93,8 @@ INTEL_G8A =				\
 	exa_wm_src_sample_argb.g8a 	\
 	exa_wm_yuv_color_balance.g8a	\
 	exa_wm_write.g8a 		\
-	exa_wm_yuv_rgb.g8a
+	exa_wm_yuv_rgb.g8a		\
+	exa_wm_clear.g8a
 
 INTEL_G8S = $(INTEL_G8A:%.g8a=%.g8s)
 
@@ -102,7 +104,8 @@ INTEL_G8B =				\
 	exa_wm_src_sample_argb.g8b 	\
 	exa_wm_yuv_color_balance.g8b	\
 	exa_wm_yuv_rgb.g8b		\
-	exa_wm_write.g8b 
+	exa_wm_write.g8b		\
+	exa_wm_clear.g8b
 
 INTEL_G9A =				\
 	exa_wm_src_affine.g9a 		\
@@ -110,7 +113,8 @@ INTEL_G9A =				\
 	exa_wm_src_sample_argb.g9a 	\
 	exa_wm_yuv_color_balance.g9a	\
 	exa_wm_write.g9a 		\
-	exa_wm_yuv_rgb.g9a
+	exa_wm_yuv_rgb.g9a		\
+	exa_wm_clear.g9a
 
 INTEL_G9I = $(INTEL_G4I)
 
@@ -122,7 +126,8 @@ INTEL_G9B =				\
 	exa_wm_src_sample_argb.g9b 	\
 	exa_wm_yuv_color_balance.g9b	\
 	exa_wm_yuv_rgb.g9b		\
-	exa_wm_write.g9b
+	exa_wm_write.g9b		\
+	exa_wm_clear.g9b
 
 TARGETS  =
 if HAVE_GEN4ASM
diff --git a/src/shaders/render/exa_wm_clear.g7i b/src/shaders/render/exa_wm_clear.g7i
new file mode 100644
index 00000000..90c8d20e
--- /dev/null
+++ b/src/shaders/render/exa_wm_clear.g7i
@@ -0,0 +1,82 @@
+/*
+ * Copyright © 2018 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ *    Xiang Haihao <haihao.xiang@intel.com>
+ */
+
+/* header */
+define(`data_port_msg_2_0',     `g112')
+define(`data_port_msg_2_1',     `g113')
+define(`data_port_msg_2_ind',   `112')
+
+mov (8) data_port_msg_2_0<1>UD g0<8,8,1>UD {align1 mask_disable};
+mov (8) data_port_msg_2_1<1>UD g1<8,8,1>UD {align1 mask_disable};
+
+/*
+ * Prepare data in g114-g115 for Red channel, g116-g117 for Green channel,
+ * g118-g119 for Blue and g120-g121 for Alpha channel
+ */
+define(`slot_r_00',     `g114')
+define(`slot_r_01',     `g115')
+define(`slot_g_00',     `g116')
+define(`slot_g_01',     `g117')
+define(`slot_b_00',     `g118')
+define(`slot_b_01',     `g119')
+define(`slot_a_00',     `g120')
+define(`slot_a_01',     `g121')
+
+mov (8) slot_r_00<1>F     0.0F { align1 mask_disable };
+mov (8) slot_r_01<1>F     0.0F { align1 mask_disable };
+
+mov (8) slot_g_00<1>F     0.0F { align1 mask_disable };
+mov (8) slot_g_01<1>F     0.0F { align1 mask_disable };
+
+mov (8) slot_b_00<1>F     0.0F { align1 mask_disable };
+mov (8) slot_b_01<1>F     0.0F { align1 mask_disable };
+
+mov (8) slot_a_00<1>F     1.0F { align1 mask_disable };
+mov (8) slot_a_01<1>F     1.0F { align1 mask_disable };
+
+send (16)
+	data_port_msg_2_ind
+	null<1>UW
+	null
+	write (
+	       0,   /* binding table index */
+	       16,  /* last render target(1) + slots 15:0(0) + msg type simd16 single source(000) */
+	       12,  /* render target write */
+	       0,   /* ignore for Ivybridge */
+	       1    /* header present */
+	)
+	mlen 10
+	rlen 0
+	{ align1 EOT };
+
+nop;
+nop;
+nop;
+nop;
+nop;
+nop;
+nop;
+nop;
diff --git a/src/shaders/render/exa_wm_clear.g8a b/src/shaders/render/exa_wm_clear.g8a
new file mode 100644
index 00000000..b6cc005e
--- /dev/null
+++ b/src/shaders/render/exa_wm_clear.g8a
@@ -0,0 +1,28 @@
+/*
+ * Copyright © 2018 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ *    Xiang Haihao <haihao.xiang@intel.com>
+ */
+
+include(`exa_wm.g4i')
+include(`exa_wm_clear.g7i')
diff --git a/src/shaders/render/exa_wm_clear.g8b b/src/shaders/render/exa_wm_clear.g8b
new file mode 100644
index 00000000..5f25e8a3
--- /dev/null
+++ b/src/shaders/render/exa_wm_clear.g8b
@@ -0,0 +1,19 @@
+   { 0x00600001, 0x2e00020c, 0x008d0000, 0x00000000 },
+   { 0x00600001, 0x2e20020c, 0x008d0020, 0x00000000 },
+   { 0x00600001, 0x2e403eec, 0x38000000, 0x00000000 },
+   { 0x00600001, 0x2e603eec, 0x38000000, 0x00000000 },
+   { 0x00600001, 0x2e803eec, 0x38000000, 0x00000000 },
+   { 0x00600001, 0x2ea03eec, 0x38000000, 0x00000000 },
+   { 0x00600001, 0x2ec03eec, 0x38000000, 0x00000000 },
+   { 0x00600001, 0x2ee03eec, 0x38000000, 0x00000000 },
+   { 0x00600001, 0x2f003eec, 0x38000000, 0x3f800000 },
+   { 0x00600001, 0x2f203eec, 0x38000000, 0x3f800000 },
+   { 0x05800031, 0x20000a40, 0x0e000e00, 0x940b1000 },
+   { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+   { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+   { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+   { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+   { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+   { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+   { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+   { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
diff --git a/src/shaders/render/exa_wm_clear.g9a b/src/shaders/render/exa_wm_clear.g9a
new file mode 100644
index 00000000..b6cc005e
--- /dev/null
+++ b/src/shaders/render/exa_wm_clear.g9a
@@ -0,0 +1,28 @@
+/*
+ * Copyright © 2018 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ *    Xiang Haihao <haihao.xiang@intel.com>
+ */
+
+include(`exa_wm.g4i')
+include(`exa_wm_clear.g7i')
diff --git a/src/shaders/render/exa_wm_clear.g9b b/src/shaders/render/exa_wm_clear.g9b
new file mode 100644
index 00000000..f37932f0
--- /dev/null
+++ b/src/shaders/render/exa_wm_clear.g9b
@@ -0,0 +1,19 @@
+   { 0x00600001, 0x2e00020c, 0x008d0000, 0x00000000 },
+   { 0x00600001, 0x2e20020c, 0x008d0020, 0x00000000 },
+   { 0x00600001, 0x2e403eec, 0x38000000, 0x00000000 },
+   { 0x00600001, 0x2e603eec, 0x38000000, 0x00000000 },
+   { 0x00600001, 0x2e803eec, 0x38000000, 0x00000000 },
+   { 0x00600001, 0x2ea03eec, 0x38000000, 0x00000000 },
+   { 0x00600001, 0x2ec03eec, 0x38000000, 0x00000000 },
+   { 0x00600001, 0x2ee03eec, 0x38000000, 0x00000000 },
+   { 0x00600001, 0x2f003eec, 0x38000000, 0x3f800000 },
+   { 0x00600001, 0x2f203eec, 0x38000000, 0x3f800000 },
+   { 0x05800031, 0x20000a40, 0x06000e00, 0x940b1000 },
+   { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+   { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+   { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+   { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+   { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+   { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+   { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+   { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },