diff options
-rw-r--r-- | src/gen9_render.c | 16 | ||||
-rw-r--r-- | src/shaders/render/Makefile.am | 30 | ||||
-rw-r--r-- | src/shaders/render/exa_wm_src_affine.g9a | 45 | ||||
-rw-r--r-- | src/shaders/render/exa_wm_src_affine.g9b | 4 | ||||
-rw-r--r-- | src/shaders/render/exa_wm_src_sample_argb.g9a | 59 | ||||
-rw-r--r-- | src/shaders/render/exa_wm_src_sample_argb.g9b | 5 | ||||
-rw-r--r-- | src/shaders/render/exa_wm_src_sample_planar.g9a | 105 | ||||
-rw-r--r-- | src/shaders/render/exa_wm_src_sample_planar.g9b | 20 | ||||
-rw-r--r-- | src/shaders/render/exa_wm_write.g9a | 82 | ||||
-rw-r--r-- | src/shaders/render/exa_wm_write.g9b | 19 | ||||
-rw-r--r-- | src/shaders/render/exa_wm_yuv_color_balance.g9a | 39 | ||||
-rw-r--r-- | src/shaders/render/exa_wm_yuv_color_balance.g9b | 15 | ||||
-rw-r--r-- | src/shaders/render/exa_wm_yuv_rgb.g9a | 32 | ||||
-rw-r--r-- | src/shaders/render/exa_wm_yuv_rgb.g9b | 13 |
14 files changed, 476 insertions, 8 deletions
diff --git a/src/gen9_render.c b/src/gen9_render.c index 3c14f692..8d361bb6 100644 --- a/src/gen9_render.c +++ b/src/gen9_render.c @@ -53,17 +53,17 @@ static const uint32_t sf_kernel_static_gen9[][4] ={ }; static const uint32_t ps_kernel_static_gen9[][4] = { -#include "shaders/render/exa_wm_src_affine.g8b" -#include "shaders/render/exa_wm_src_sample_planar.g8b" -#include "shaders/render/exa_wm_yuv_color_balance.g8b" -#include "shaders/render/exa_wm_yuv_rgb.g8b" -#include "shaders/render/exa_wm_write.g8b" +#include "shaders/render/exa_wm_src_affine.g9b" +#include "shaders/render/exa_wm_src_sample_planar.g9b" +#include "shaders/render/exa_wm_yuv_color_balance.g9b" +#include "shaders/render/exa_wm_yuv_rgb.g9b" +#include "shaders/render/exa_wm_write.g9b" }; static const uint32_t ps_subpic_kernel_static_gen9[][4] = { -#include "shaders/render/exa_wm_src_affine.g8b" -#include "shaders/render/exa_wm_src_sample_argb.g8b" -#include "shaders/render/exa_wm_write.g8b" +#include "shaders/render/exa_wm_src_affine.g9b" +#include "shaders/render/exa_wm_src_sample_argb.g9b" +#include "shaders/render/exa_wm_write.g9b" }; diff --git a/src/shaders/render/Makefile.am b/src/shaders/render/Makefile.am index 90243519..dfe9e6b4 100644 --- a/src/shaders/render/Makefile.am +++ b/src/shaders/render/Makefile.am @@ -103,6 +103,26 @@ INTEL_G8B = \ exa_wm_yuv_rgb.g8b \ exa_wm_write.g8b +INTEL_G9A = \ + exa_wm_src_affine.g9a \ + exa_wm_src_sample_planar.g9a \ + exa_wm_src_sample_argb.g9a \ + exa_wm_yuv_color_balance.g9a \ + exa_wm_write.g9a \ + exa_wm_yuv_rgb.g9a + +INTEL_G9I = $(INTEL_G4I) + +INTEL_G9S = $(INTEL_G9A:%.g9a=%.g9s) + +INTEL_G9B = \ + exa_wm_src_affine.g9b \ + exa_wm_src_sample_planar.g9b \ + exa_wm_src_sample_argb.g9b \ + exa_wm_yuv_color_balance.g9b \ + exa_wm_yuv_rgb.g9b \ + exa_wm_write.g9b + TARGETS = if HAVE_GEN4ASM TARGETS += $(INTEL_G4B) @@ -111,6 +131,7 @@ TARGETS += $(INTEL_G6B) TARGETS += $(INTEL_G7B) TARGETS += $(INTEL_G7B_HASWELL) TARGETS += $(INTEL_G8B) +TARGETS += $(INTEL_G9B) endif all-local: $(TARGETS) @@ -147,6 +168,12 @@ $(INTEL_G8S): $(INTEL_G8A) $(INTEL_G8I) .g8s.g8b: $(AM_V_GEN)$(GEN4ASM) -g 8 -o $@ $< +$(INTEL_G9S): $(INTEL_G9A) $(INTEL_G9I) +.g9a.g9s: + $(AM_V_GEN)m4 $< > $@ +.g9s.g9b: + $(AM_V_GEN)$(GEN4ASM) -g 9 -o $@ $< + endif CLEANFILES = \ @@ -154,6 +181,7 @@ CLEANFILES = \ $(INTEL_G6S) \ $(INTEL_G7S) \ $(INTEL_G8S) \ + $(INTEL_G9S) \ $(NULL) EXTRA_DIST = \ @@ -168,6 +196,8 @@ EXTRA_DIST = \ $(INTEL_G7B_HASWELL) \ $(INTEL_G8A) \ $(INTEL_G8B) \ + $(INTEL_G9A)) \ + $(INTEL_G9B) \ $(NULL) # Extra clean files so that maintainer-clean removes *everything* diff --git a/src/shaders/render/exa_wm_src_affine.g9a b/src/shaders/render/exa_wm_src_affine.g9a new file mode 100644 index 00000000..832f70c4 --- /dev/null +++ b/src/shaders/render/exa_wm_src_affine.g9a @@ -0,0 +1,45 @@ +/* + * Copyright © 2014 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + */ + +/* + * Fragment to compute src u/v values + */ +include(`exa_wm.g4i') + +define(`ul', `g66') +define(`uh', `g67') +define(`vl', `g68') +define(`vh', `g69') + +define(`bl', `g2.0<8,8,1>F') +define(`bh', `g4.0<8,8,1>F') + + +/* U */ +pln (8) ul<1>F a0_a_x bl { align1 }; /* pixel 0-7 */ +pln (8) uh<1>F a0_a_x bh { align1 }; /* pixel 8-15 */ + +/* V */ +pln (8) vl<1>F a0_a_y bl { align1 }; /* pixel 0-7 */ +pln (8) vh<1>F a0_a_y bh { align1 }; /* pixel 8-15 */ diff --git a/src/shaders/render/exa_wm_src_affine.g9b b/src/shaders/render/exa_wm_src_affine.g9b new file mode 100644 index 00000000..f5f9eca1 --- /dev/null +++ b/src/shaders/render/exa_wm_src_affine.g9b @@ -0,0 +1,4 @@ + { 0x0060005a, 0x28403ae8, 0x3a000140, 0x008d0040 }, + { 0x0060005a, 0x28603ae8, 0x3a000140, 0x008d0080 }, + { 0x0060005a, 0x28803ae8, 0x3a000150, 0x008d0040 }, + { 0x0060005a, 0x28a03ae8, 0x3a000150, 0x008d0080 }, diff --git a/src/shaders/render/exa_wm_src_sample_argb.g9a b/src/shaders/render/exa_wm_src_sample_argb.g9a new file mode 100644 index 00000000..ca57ea60 --- /dev/null +++ b/src/shaders/render/exa_wm_src_sample_argb.g9a @@ -0,0 +1,59 @@ +/* + * Copyright © 2014 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Authors: + * Wang Zhenyu <zhenyu.z.wang@intel.com> + * Keith Packard <keithp@keithp.com> + * Zhao Yakui <yakui.zhao@intel.com> + */ + +/* Sample the src surface */ + +include(`exa_wm.g4i') + +/* Ivybridge uses GRFs in SEND instruction */ +define(`src_msg_gen8', `g65') +define(`src_msg_ind_gen8',`65') + +/* subpicture global alpha */ +define(`global_alpha', `r6.0<0,1,0>f') + +/* prepare sampler read back gX register, which would be written back to output */ + +/* use simd16 sampler, param 0 is u, param 1 is v. */ +/* 'payload' loading, assuming tex coord start from g4 */ + +/* load argb */ +mov (1) g0.8<1>UD 0x00000000UD { align1 mask_disable }; +mov (8) src_msg_gen8<1>UD g0<8,8,1>UD { align1 mask_disable }; + +/* src_msg will be copied with g0, as it contains send desc */ +/* emit sampler 'send' cmd */ +send (16) src_msg_ind_gen8 /* msg reg index */ + src_sample_base<1>UW /* readback */ + null + sampler (1,0,F) /* sampler message description, (binding_table,sampler_index,datatype) + /* here(src->dst) we should use src_sampler and src_surface */ + mlen 5 rlen 8 { align1 }; /* required message len 5, readback len 8 */ + +mul (8) src_sample_a_01<1>f src_sample_a_01<8,8,1>f global_alpha { align1 mask_disable }; +mul (8) src_sample_a_23<1>f src_sample_a_23<8,8,1>f global_alpha { align1 mask_disable }; diff --git a/src/shaders/render/exa_wm_src_sample_argb.g9b b/src/shaders/render/exa_wm_src_sample_argb.g9b new file mode 100644 index 00000000..5cd181e3 --- /dev/null +++ b/src/shaders/render/exa_wm_src_sample_argb.g9b @@ -0,0 +1,5 @@ + { 0x00000001, 0x2008060c, 0x00000000, 0x00000000 }, + { 0x00600001, 0x2820020c, 0x008d0000, 0x00000000 }, + { 0x02800031, 0x21c00a48, 0x06000820, 0x0a8c0001 }, + { 0x00600041, 0x22803aec, 0x3a8d0280, 0x000000c0 }, + { 0x00600041, 0x22a03aec, 0x3a8d02a0, 0x000000c0 }, diff --git a/src/shaders/render/exa_wm_src_sample_planar.g9a b/src/shaders/render/exa_wm_src_sample_planar.g9a new file mode 100644 index 00000000..f5369cae --- /dev/null +++ b/src/shaders/render/exa_wm_src_sample_planar.g9a @@ -0,0 +1,105 @@ +/* + * Copyright © 2013 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Authors: + * Wang Zhenyu <zhenyu.z.wang@intel.com> + * Keith Packard <keithp@keithp.com> + * Zhao Yakui <yakui.zhao@intel.com> + */ + +/* Sample the src surface in planar format */ + +include(`exa_wm.g4i') + +/* Ivybridge uses GRFs in SEND instruction */ +define(`src_msg_gen8', `g65') +define(`src_msg_ind_gen8',`65') +/* UV flag */ +define(`uv_flag', `g6.0<0,1,0>UW') + +/* prepare sampler read back gX register, which would be written back to output */ + +/* use simd16 sampler, param 0 is u, param 1 is v. */ +/* 'payload' loading, assuming tex coord start from g4 */ +cmp.e.f0.0 (1) null uv_flag 0x1UW {align1}; +(f0.0) jmpi INTERLEAVED_UV; + +cmp.e.f0.0 (1) null uv_flag 0x2UW {align1}; +(f0.0) jmpi CONSTANT_UV; + +/* load r */ +mov (1) g0.8<1>UD 0x0000e000UD { align1 mask_disable }; +mov (8) src_msg_gen8<1>UD g0<8,8,1>UD { align1 mask_disable }; + +/* emit sampler 'send' cmd */ + +/* sample U (Cr) */ +send (16) src_msg_ind_gen8 /* msg reg index */ + src_sample_g<1>UW /* readback */ + null + sampler (3,2,F) /* sampler message description, (binding_table,sampler_index,datatype) + /* here(src->dst) we should use src_sampler and src_surface */ + mlen 5 rlen 2 { align1 }; /* required message len 5, readback len 8 */ + +/* sample V (Cb) */ +mov (1) g0.8<1>UD 0x0000e000UD { align1 mask_disable }; +mov (8) src_msg_gen8<1>UD g0<8,8,1>UD { align1 mask_disable }; + +send (16) src_msg_ind_gen8 /* msg reg index */ + src_sample_b<1>UW /* readback */ + null + sampler (5,4,F) /* sampler message description, (binding_table,sampler_index,datatype) + /* here(src->dst) we should use src_sampler and src_surface */ + mlen 5 rlen 2 { align1 }; /* required message len 5, readback len 8 */ + +jmpi SAMPLE_Y; + +CONSTANT_UV: +mov (16) src_sample_g<1>f 0.5f { compr align1 mask_disable }; +mov (16) src_sample_b<1>f 0.5f { compr align1 mask_disable }; + +jmpi SAMPLE_Y; + +INTERLEAVED_UV: +mov (1) g0.8<1>UD 0x0000c000UD { align1 mask_disable }; +mov (8) src_msg_gen8<1>UD g0<8,8,1>UD { align1 mask_disable }; + +/* sample UV (CrCb) */ +send (16) src_msg_ind_gen8 /* msg reg index */ + src_sample_g<1>UW /* readback */ + null + sampler (3,2,F) /* sampler message description, (binding_table,sampler_index,datatype) + /* here(src->dst) we should use src_sampler and src_surface */ + mlen 5 rlen 4 { align1 }; /* required message len 5, readback len 8 */ + + +SAMPLE_Y: +mov (1) g0.8<1>UD 0x0000e000UD { align1 mask_disable }; +mov (8) src_msg_gen8<1>UD g0<8,8,1>UD { align1 mask_disable }; + +/* sample Y */ +send (16) src_msg_ind_gen8 /* msg reg index */ + src_sample_r<1>UW /* readback */ + null + sampler (1,0,F) /* sampler message description, (binding_table,sampler_index,datatype) + /* here(src->dst) we should use src_sampler and src_surface */ + mlen 5 rlen 2 { align1 }; /* required message len 5, readback len 8 */ diff --git a/src/shaders/render/exa_wm_src_sample_planar.g9b b/src/shaders/render/exa_wm_src_sample_planar.g9b new file mode 100644 index 00000000..45e28b0a --- /dev/null +++ b/src/shaders/render/exa_wm_src_sample_planar.g9b @@ -0,0 +1,20 @@ + { 0x01000010, 0x200012e0, 0x160000c0, 0x00010001 }, + { 0x00010020, 0x34000000, 0x0e001400, 0x000000c0 }, + { 0x01000010, 0x200012e0, 0x160000c0, 0x00020002 }, + { 0x00010020, 0x34000000, 0x0e001400, 0x00000070 }, + { 0x00000001, 0x2008060c, 0x00000000, 0x0000e000 }, + { 0x00600001, 0x2820020c, 0x008d0000, 0x00000000 }, + { 0x02800031, 0x22000a48, 0x06000820, 0x0a2c0203 }, + { 0x00000001, 0x2008060c, 0x00000000, 0x0000e000 }, + { 0x00600001, 0x2820020c, 0x008d0000, 0x00000000 }, + { 0x02800031, 0x22400a48, 0x06000820, 0x0a2c0405 }, + { 0x00000020, 0x34000000, 0x0e001400, 0x00000060 }, + { 0x00800001, 0x22003eec, 0x38000000, 0x3f000000 }, + { 0x00800001, 0x22403eec, 0x38000000, 0x3f000000 }, + { 0x00000020, 0x34000000, 0x0e001400, 0x00000030 }, + { 0x00000001, 0x2008060c, 0x00000000, 0x0000c000 }, + { 0x00600001, 0x2820020c, 0x008d0000, 0x00000000 }, + { 0x02800031, 0x22000a48, 0x06000820, 0x0a4c0203 }, + { 0x00000001, 0x2008060c, 0x00000000, 0x0000e000 }, + { 0x00600001, 0x2820020c, 0x008d0000, 0x00000000 }, + { 0x02800031, 0x21c00a48, 0x06000820, 0x0a2c0001 }, diff --git a/src/shaders/render/exa_wm_write.g9a b/src/shaders/render/exa_wm_write.g9a new file mode 100644 index 00000000..5275cdc7 --- /dev/null +++ b/src/shaders/render/exa_wm_write.g9a @@ -0,0 +1,82 @@ +/* + * Copyright © 2014 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + */ + +include(`exa_wm.g4i') + +/* header */ +define(`data_port_msg_2_0', `g112') +define(`data_port_msg_2_1', `g113') +define(`data_port_msg_2_ind', `112') + +mov (8) data_port_msg_2_0<1>UD g0<8,8,1>UD {align1 mask_disable}; +mov (8) data_port_msg_2_1<1>UD g1<8,8,1>UD {align1 mask_disable}; + +/* + * Prepare data in g114-g115 for Red channel, g116-g117 for Green channel, + * g118-g119 for Blue and g120-g121 for Alpha channel + */ +define(`slot_r_00', `g114') +define(`slot_r_01', `g115') +define(`slot_g_00', `g116') +define(`slot_g_01', `g117') +define(`slot_b_00', `g118') +define(`slot_b_01', `g119') +define(`slot_a_00', `g120') +define(`slot_a_01', `g121') + +mov (8) slot_r_00<1>F src_sample_r_01<8,8,1>F { align1 mask_disable }; +mov (8) slot_r_01<1>F src_sample_r_23<8,8,1>F { align1 mask_disable }; + +mov (8) slot_g_00<1>F src_sample_g_01<8,8,1>F { align1 mask_disable }; +mov (8) slot_g_01<1>F src_sample_g_23<8,8,1>F { align1 mask_disable }; + +mov (8) slot_b_00<1>F src_sample_b_01<8,8,1>F { align1 mask_disable }; +mov (8) slot_b_01<1>F src_sample_b_23<8,8,1>F { align1 mask_disable }; + +mov (8) slot_a_00<1>F src_sample_a_01<8,8,1>F { align1 mask_disable }; +mov (8) slot_a_01<1>F src_sample_a_23<8,8,1>F { align1 mask_disable }; + +send (16) + data_port_msg_2_ind + null<1>UW + null + write ( + 0, /* binding table index */ + 16, /* last render target(1) + slots 15:0(0) + msg type simd16 single source(000) */ + 12, /* render target write */ + 0, /* ignore for Ivybridge */ + 1 /* header present */ + ) + mlen 10 + rlen 0 + { align1 EOT }; + +nop; +nop; +nop; +nop; +nop; +nop; +nop; +nop; diff --git a/src/shaders/render/exa_wm_write.g9b b/src/shaders/render/exa_wm_write.g9b new file mode 100644 index 00000000..e625b9d0 --- /dev/null +++ b/src/shaders/render/exa_wm_write.g9b @@ -0,0 +1,19 @@ + { 0x00600001, 0x2e00020c, 0x008d0000, 0x00000000 }, + { 0x00600001, 0x2e20020c, 0x008d0020, 0x00000000 }, + { 0x00600001, 0x2e403aec, 0x008d01c0, 0x00000000 }, + { 0x00600001, 0x2e603aec, 0x008d01e0, 0x00000000 }, + { 0x00600001, 0x2e803aec, 0x008d0200, 0x00000000 }, + { 0x00600001, 0x2ea03aec, 0x008d0220, 0x00000000 }, + { 0x00600001, 0x2ec03aec, 0x008d0240, 0x00000000 }, + { 0x00600001, 0x2ee03aec, 0x008d0260, 0x00000000 }, + { 0x00600001, 0x2f003aec, 0x008d0280, 0x00000000 }, + { 0x00600001, 0x2f203aec, 0x008d02a0, 0x00000000 }, + { 0x05800031, 0x20000a40, 0x06000e00, 0x940b1000 }, + { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, + { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, + { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, + { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, + { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, + { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, + { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, + { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, diff --git a/src/shaders/render/exa_wm_yuv_color_balance.g9a b/src/shaders/render/exa_wm_yuv_color_balance.g9a new file mode 100644 index 00000000..511e3f31 --- /dev/null +++ b/src/shaders/render/exa_wm_yuv_color_balance.g9a @@ -0,0 +1,39 @@ +/* + * Copyright © 2014 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Authors: + * Haihao Xiang <haihao.xiang@intel.com> + * Zhao Yakui <yakui.zhao@intel.com> + * + */ + +include(`exa_wm.g4i') + +/* Color Balance parameters */ +define(`skip_color_balance', `g6.2<0,1,0>uw') +define(`contrast', `g6.16<0,1,0>f') +define(`brightness', `g6.20<0,1,0>f') +define(`cos_c_s', `g6.24<0,1,0>f') +define(`sin_c_s', `g6.28<0,1,0>f') +define(`sin_c_s_t', `g6.28') + +include(`exa_wm_yuv_color_balance.gxa') diff --git a/src/shaders/render/exa_wm_yuv_color_balance.g9b b/src/shaders/render/exa_wm_yuv_color_balance.g9b new file mode 100644 index 00000000..5dc2c8bc --- /dev/null +++ b/src/shaders/render/exa_wm_yuv_color_balance.g9b @@ -0,0 +1,15 @@ + { 0x01000010, 0x200012e0, 0x160000c2, 0x00010001 }, + { 0x00010020, 0x34000000, 0x0e001400, 0x000000d0 }, + { 0x00800040, 0x24003ae8, 0x3e8d01c0, 0xbd808081 }, + { 0x00800041, 0x24003ae8, 0x3a8d0400, 0x000000d0 }, + { 0x00800040, 0x24003ae8, 0x3a8d0400, 0x000000d4 }, + { 0x00800040, 0x21c03ae8, 0x3e8d0400, 0x3d808081 }, + { 0x00800040, 0x24803ae8, 0x3e8d0200, 0xbf008084 }, + { 0x00800040, 0x24403ae8, 0x3e8d0240, 0xbf008084 }, + { 0x00800001, 0x24003ee0, 0x38000000, 0x3f008084 }, + { 0x00800048, 0x24003ae0, 0x3a8d0440, 0x000000dc }, + { 0x00800048, 0x22003ae8, 0x3a8d0480, 0x000000d8 }, + { 0x00000041, 0x20dc3ae8, 0x3e0000dc, 0xbf800000 }, + { 0x00800001, 0x24003ee0, 0x38000000, 0x3f008084 }, + { 0x00800048, 0x24003ae0, 0x3a8d0480, 0x000000dc }, + { 0x00800048, 0x22403ae8, 0x3a8d0440, 0x000000d8 }, diff --git a/src/shaders/render/exa_wm_yuv_rgb.g9a b/src/shaders/render/exa_wm_yuv_rgb.g9a new file mode 100644 index 00000000..e5f82c65 --- /dev/null +++ b/src/shaders/render/exa_wm_yuv_rgb.g9a @@ -0,0 +1,32 @@ +/* + * Copyright © 2014 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Authors: + * Keith Packard <keithp@keithp.com> + * Eric Anholt <eric@anholt.net> + * Zhao Yakui <yakui.zhao@intel.com> + * + */ + +include(`exa_wm.g4i') +include(`exa_yuv_gen6.g4i') +include(`exa_yuv_rgb.gxa') diff --git a/src/shaders/render/exa_wm_yuv_rgb.g9b b/src/shaders/render/exa_wm_yuv_rgb.g9b new file mode 100644 index 00000000..6b6b4d1c --- /dev/null +++ b/src/shaders/render/exa_wm_yuv_rgb.g9b @@ -0,0 +1,13 @@ + { 0x00800040, 0x22c03ae8, 0x3a8d01c0, 0x000000ec }, + { 0x00800040, 0x23003ae8, 0x3a8d0200, 0x000000fc }, + { 0x00800040, 0x23403ae8, 0x3a8d0240, 0x0000010c }, + { 0x00800041, 0x24003ae0, 0x3a8d02c0, 0x000000e0 }, + { 0x00800048, 0x24003ae0, 0x3a8d0300, 0x000000e4 }, + { 0x80800048, 0x21c03ae8, 0x3a8d0340, 0x000000e8 }, + { 0x00800041, 0x24003ae0, 0x3a8d02c0, 0x000000f0 }, + { 0x00800048, 0x24003ae0, 0x3a8d0300, 0x000000f4 }, + { 0x80800048, 0x22003ae8, 0x3a8d0340, 0x000000f8 }, + { 0x00800041, 0x24003ae0, 0x3a8d02c0, 0x00000100 }, + { 0x00800048, 0x24003ae0, 0x3a8d0300, 0x00000104 }, + { 0x80800048, 0x22403ae8, 0x3a8d0340, 0x00000108 }, + { 0x00800001, 0x22803ee8, 0x38000000, 0x3f800000 }, |