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* vpp/avs: fix license terms (MIT).stagingGwenole Beauchesne2015-07-072-28/+36
| | | | | Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com> (cherry picked from commit fb5e1cd86047e2683f169cd52cc27861447321cf)
* Decode: Free the allocated internal surface used by JPEG to avoid memory leakZhao Yakui2015-05-203-0/+26
| | | | | | | Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> Signed-off-by: Sean V Kelley <seanvk@posteo.de> Tested-by: Sean V Kelley <seanvk@posteo.de> (cherry picked from commit 8dda0650b55c467200c34ada127b5d9b54edea5c)
* Add support for HEVC decoding on CHVSean V Kelley2015-02-251-2/+3
| | | | | | | | We can re-use SKL HEVC decode pipeline Signed-off-by: Sean V Kelley <seanvk@posteo.de> Cc: haihao.xiang@intel.com Cc: focus.luo@intel.com
* MPEG2 ENC: Remove gen9 pak pipeline codeZhong Li2015-02-251-746/+3
| | | | | | | SKL pak pipeline of mpeg2 encoding is same as gen8, so remove the redundant code Signed-off-by: Zhong Li <zhong.li@intel.com>
* VP8 DEC: Change error concealment methodZhong Li2015-02-251-3/+1
| | | | | | | Use intra prediciton as error concealment method, instead of inter P copy. Signed-off-by: Zhong Li <zhong.li@intel.com>
* Disable the context check to avoid JPEG ENC failedQu,Pengfei2015-02-021-31/+1
| | | | | https://bugs.freedesktop.org/show_bug.cgi?id=88728 Signed-off-by: Qu,Pengfei <Pengfei.Qu@intel.com>
* Just Style alignmentQu,Pengfei2015-01-154-486/+486
| | | | Signed-off-by: Qu,Pengfei <Pengfei.Qu@intel.com>
* HEVC ENC:Added HEVC support in API functionQu,Pengfei2015-01-152-21/+96
| | | | Signed-off-by: Qu,Pengfei <Pengfei.Qu@intel.com>
* HEVC ENC:Added pipeline initQu,Pengfei2015-01-151-1/+73
| | | | Signed-off-by: Qu,Pengfei <Pengfei.Qu@intel.com>
* HEVC ENC:Added VME pipelineQu,Pengfei2015-01-153-0/+725
| | | | Signed-off-by: Qu,Pengfei <Pengfei.Qu@intel.com>
* HEVC ENC:Added PAK pipelineQu,Pengfei2015-01-153-0/+2636
| | | | | | Signed-off-by: Qu,Pengfei <Pengfei.Qu@intel.com> [Fix PAK-BSE data start offset in HCP_SLICE_STATE] Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
* HEVC ENC:Added slice header generated internallyQu,Pengfei2015-01-153-3/+500
| | | | Signed-off-by: Qu,Pengfei <Pengfei.Qu@intel.com>
* HEVC ENC:Added PAK context for HEVCQu,Pengfei2015-01-152-0/+238
| | | | Signed-off-by: Qu,Pengfei <Pengfei.Qu@intel.com>
* VP8 HWEnc: Add BSW VP8 HWEnc supportZhong Li2015-01-1513-977/+2455
| | | | | | Add BSW vp8 encoding support, and let SKL and BDW use the same PAK pipeline. Signed-off-by: Zhong Li <zhong.li@intel.com>
* VP8 HWEnc: declare copyright and license of vp8_probs.hZhong Li2015-01-154-0/+194
| | | | Signed-off-by: Zhong Li <zhong.li@intel.com>
* VP8 HWEnc: vp8 encode quality optimizationZhong Li2015-01-159-47/+255
| | | | | | | | | 1. Add mv and mode cost calc 2. Support 16x16 and 4x4 intra prediction 3. Support multi-mode intar prediction 4. Support 16x16 New_MV mode inter prediction Signed-off-by: Zhong Li <zhong.li@intel.com>
* VP8 HWEnc: Calc vp8 coded size by internal bufferZhong Li2015-01-153-19/+36
| | | | Signed-off-by: Zhong Li <zhong.li@intel.com>
* VP8 HWEnc: Add P frame encoding supportZhong Li2015-01-157-50/+1136
| | | | Signed-off-by: Zhong Li <zhong.li@intel.com>
* VP8 HWEnc: Build VP8 PAK pipeline and enabling I frameZhong Li2015-01-159-6/+1303
| | | | Signed-off-by: Zhong Li <zhong.li@intel.com>
* VP8 HWEnc: Build vp8 gen9 encoding vme pipelineZhong Li2015-01-154-54/+213
| | | | Signed-off-by: Zhong Li <zhong.li@intel.com>
* VP8 HWEnc: Add vp8 gen9 intra frame encoding shaderZhong Li2015-01-155-3/+283
| | | | Signed-off-by: Zhong Li <zhong.li@intel.com>
* Update license header for some shadersXiang, Haihao2015-01-14323-973/+9983
| | | | | Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> (cherry picked from commit 7e444da6f69a642267fbd16257d0e8615d36173c)
* BDW+: disable SGVSJoe Konno2015-01-143-0/+9
| | | | | | | | | | | BDW introduces separate packets for controlling instancing and system generated values (eg vertex id and instance id). We don't use instancing, but still need to disable sgvs to avoid undefined behaviour when some other driver (mesa) uses it. Signed-off-by: Joe Konno <joe.konno@intel.com> Signed-off-by: Kristian Høgsberg <krh@bitplanet.net> Reviewed-by: Daniel Charles <daniel.charles@intel.com>
* i965 render: Explicitly disable instancing for vertex elements on SkylakeZhao Yakui2015-01-121-0/+8
| | | | | | | | | | We really should guarantee that vertex elements non-instanced, especially since we don't use our own hardware context - other programs can change this on us. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Sean V Kelley <seanvk@posteo.de> Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
* i965 render: Explicitly disable instancing for vertex elements on Gen8Kenneth Graunke2015-01-122-0/+11
| | | | | | | | | We really should guarantee that vertex elements non-instanced, especially since we don't use our own hardware context - other programs can change this on us. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Sean V Kelley <seanvk@posteo.de>
* Fix segmentation fault caused by 4711da5Xiang, Haihao2015-01-091-3/+4
| | | | | | | | The corresponding pointer is NULL if VAProcFilterSkinToneEnhancement isn't enabled in the pipeline Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
* Fix the broken attribute setting of i965_GetConfigAttribZhao Yakui2015-01-071-0/+5
| | | | | | | | Now the some attributes are incorrectly reported. It is not supported while VA_ATTRIB_NOT_SUPPORTED flag is not returned. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> Reviewed-by: Xiang Haihao <haihao.xiang@intel.com>
* Use libdrm to get device idZhenyu Wang2014-12-291-2/+2
| | | | | | | | | | | | | Instead of call ioctl by ourself, use libdrm interface to get device id. This not only saves one ioctl call as is done when gem bufmgr init. It also allows to use libdrm's device id override helper envionment "INTEL_DEVID_OVERRIDE". If you override device id combined with aub dump enable, you can get aub file to debug it under emulator for any device that you might not have real HW metal. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
* Add new debug option for aub dumpZhenyu Wang2014-12-292-0/+7
| | | | | | | New VA debug option to dump aub file. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
* Remove the check against obj_config->profileXiang, Haihao2014-12-241-22/+0
| | | | | | | | The profile has been validated when creating the corresponding config, it fixes a JPEG decode regression on non-CHV as well. Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> (cherry picked from commit f2a34f94c57e1f7ce975b2068fb087df84b92e3a)
* Remove two fields from struct i965_render_stateXiang, Haihao2014-12-242-8/+0
| | | | | | | | | | They are useless now Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> (cherry picked from commit 89238b2f4946f3bb40aa3ffde3c6115fe97b9ca5) Conflicts: src/i965_drv_video.c
* Remove the check against render_state->interleaved_uv in i965_sw_getimage()Xiang, Haihao2014-12-241-6/+0
| | | | | | | | The surface and image have the same fourcc now, it is unnecessary to check it is interleaved. Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> (cherry picked from commit bea75d885ded5aaeb3e4bb8a561abd0e085bfeb5)
* Return error when trying to decoding an interlaced VC-1 videoXiang, Haihao2014-12-241-1/+6
| | | | | | | | https://bugs.freedesktop.org/show_bug.cgi?id=77386 Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> Reviewed-by: Zhao Yakui <yakui.zhao@intel.com> (cherry picked from commit a36f24198b46cba00a1d09f8c70dc86f36d98022)
* Rendering: Align the origin coordinate of internal buffer during AVS ↵Zhao, Yakui2014-12-243-7/+20
| | | | | | | | | | | | conversion to fix greenline The video post-processing is based on 16x16 and will be called by vaPutsurface under some scenario. But Sometimes the region of internal buffer is not aligned during VPP AVS conversion. In such case the greenline will appear on some regions. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> (cherry picked from commit 8e34fb34ed402811e512f9d41b14345f3795bac5)
* vpp: fix check for non-linear anamorphic scaling on Sandybridge.Gwenole Beauchesne2014-12-241-29/+13
| | | | | | | | | Fix pp_nv12_avs_initialize() to disable non-linear anamorphic scaling when not actually requested on Sandybridge. This is now the main entry point for advanced video scaling there, so the actual scaling mode is checked for beforehand. Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
* vpp: enable advanced video scaling in VPP pipelines too.Gwenole Beauchesne2014-12-244-11/+35
| | | | | | | | | | | | Honour advanced video scaling. i.e. propagate vaPutSurface() scaling flags, but also VPP filter flags. Also enable the sharp 8x8 filter for high-quality scaling options, while adaptive video scaling is disabled (bypassed) for now. Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com> Conflicts: src/gen75_vpp_vebox.c
* vpp: drop internal postprocessing (I965_PP_xxx) flags.Gwenole Beauchesne2014-12-248-81/+34
| | | | | | | | | | | | | | | | | Exclusively use VA-API defined video processing flags, instead of yet redefining another set with limited use. This means that we can use scaling, colorspace and picture structure flags as is, without an extra layer of conversion. Drop I965_PP_FLAG_MCDI (motion compensated deinterlacing), which was never set. Dropped the associated dead code, which was never used. And, anyway, advanced deinterlacing modes shall go through the explcit VPP interfaces. Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com> Conflicts: src/gen75_vpp_vebox.c
* vpp: cache calculation of AVS coefficients.Gwenole Beauchesne2014-12-245-22/+56
| | | | | | | | If scaling parameters don't change, i.e. if the same scaling algorithm and factors are used, there is no point in calculating the filter coefficients again. So, just cache them into the existing AVS context. Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
* vpp: validate AVS filter coefficients for debugging purposes.Gwenole Beauchesne2014-12-244-2/+95
| | | | | | | | Make sure the newly calculated filter coefficients fall into the HW accepted range of values. This normally should not be an issue with the current configuration / scaling algorithms though. Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
* vpp: add support for high-quality scaling.Gwenole Beauchesne2014-12-241-0/+92
| | | | | | | | | | | Add support for high-quality scaling during video processing. This is enabled with the VA_FILTER_SCALING_HQ filter flag. The algorithm used for that is based on a Lanczos convolution kernel: 3 lobes on either side for luma samples, and 2 lobes on either side for chroma samples. v2: fixed rounding precision for normalized coefficients. Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
* vpp: factor out calculation of AVS coefficients.Gwenole Beauchesne2014-12-245-108/+408
| | | | | | | | | | | | | | Split calculation of AVS coefficients into separate helper functions in view to supporting alternate algorithms, but we stick to bilinear interpolation for now. Actually fix bilinear filtering coefficients if the sharp 8x8 filter is used. This is still disabled by default though. Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com> Conflicts: src/gen8_post_processing.c
* vpp: fix AVS coefficients for Broadwell.Gwenole Beauchesne2014-12-242-44/+96
| | | | | | | | Fix AVS filter coefficients for Broadwell. At least, we now address the expected entry in the table but the actual value is still not viable enough. Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
* vpp: fix adaptive filter for all channels flag (< Haswell).Gwenole Beauchesne2014-12-242-13/+33
| | | | | | | | | | | | | | | The "Adaptive filter for all channels" bit for AVS on Ironlake up to including Ivybridge/Baytrail is not located in DW137, but rather in the first table of coefficients for chroma samples. Thus, split the SAMPLER_STATE_8x8 message DW137 into parts relevant to Haswell and newer generations ("hsw"), and to the legacy platforms down to Ironlake ("ilk"). Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com> Conflicts: src/i965_post_processing.c
* Use intel_batchbuffer_free() to free a batch bufferXiang, Haihao2014-12-231-1/+2
| | | | | | Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> Reviewed-by: Zhao, Yakui <yakui.zhao@intel.com> (cherry picked from commit b5d6d9d425a6d539b27d22992bda05f79d1a0622)
* Fix misused dri_bo_reference()Xiang, Haihao2014-12-231-4/+0
| | | | | | | | | | The object returned from dri_bo_alloc() has been referenced. This commit fixes https://bugs.freedesktop.org/show_bug.cgi?id=86913 Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> Reviewed-by: Zhao, Yakui <yakui.zhao@intel.com> (cherry picked from commit aa10929df05ba1668cce3960fe03be2c53e9314b)
* Fix the build of H.264 encoding shaders for SKLXiang, Haihao2014-12-232-7/+34
| | | | | | Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> Reviewed-by: Zhao, Yakui <yakui.zhao@intel.com> (cherry picked from commit 09a6b00f85417b8613d1ac6c1742e891e351cba4)
* Add sharpening shaders for SKLXiang, Haihao2014-12-196-4/+1202
| | | | Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
* STDE Optimization: Added code to support optimization of Skin Tone Detection ↵Sirisha Muppavarapu2014-12-161-79/+356
| | | | and Enhancement for stde factors 0(default), 3, 6, and 9.
* Add support for quality level for H.264 encoding on SKLXiang, Haihao2014-12-131-8/+13
| | | | Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
* Cleanup packed header insertion for MVC encodingXiang, Haihao2014-12-131-125/+16
| | | | Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
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