i965_drv_video/encode: remove all intra data in inter shader

Need to revert this commit if select inter-intra mixed mode for P/B frame

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

2 files changed, 23 insertions, 46 deletions

diff --git a/i965_drv_video/shaders/vme/inter_frame.asm b/i965_drv_video/shaders/vme/inter_frame.asm
index d5892b4..e374ea8 100644
--- a/i965_drv_video/shaders/vme/inter_frame.asm
+++ b/i965_drv_video/shaders/vme/inter_frame.asm
@@ -140,21 +140,21 @@ mov  (16) tmp_reg2.0<1>:UD      0x0:UD {align1};
  * Media Read Message -- fetch neighbor edge pixels 
  */
 /* ROW */
-mul  (2) tmp_reg0.0<1>:D        orig_xy_ub<2,2,1>:UB 16:UW {align1};    /* (x, y) * 16 */
-add  (1) tmp_reg0.0<1>:D        tmp_reg0.0<0,1,0>:D -8:W {align1};     /* X offset */
-add  (1) tmp_reg0.4<1>:D        tmp_reg0.4<0,1,0>:D -1:W {align1};     /* Y offset */ 
-mov  (1) tmp_reg0.8<1>:UD       BLOCK_32X1 {align1};
-mov  (1) tmp_reg0.20<1>:UB      thread_id_ub {align1};                  /* dispatch id */
-mov  (8) msg_reg0.0<1>:UD       tmp_reg0.0<8,8,1>:UD {align1};        
-send (16) 0 INEP_ROW null read(BIND_IDX_INEP, 0, 0, 4) mlen 1 rlen 1 {align1};
+// mul  (2) tmp_reg0.0<1>:D        orig_xy_ub<2,2,1>:UB 16:UW {align1};    /* (x, y) * 16 */
+// add  (1) tmp_reg0.0<1>:D        tmp_reg0.0<0,1,0>:D -8:W {align1};     /* X offset */
+// add  (1) tmp_reg0.4<1>:D        tmp_reg0.4<0,1,0>:D -1:W {align1};     /* Y offset */ 
+// mov  (1) tmp_reg0.8<1>:UD       BLOCK_32X1 {align1};
+// mov  (1) tmp_reg0.20<1>:UB      thread_id_ub {align1};                  /* dispatch id */
+// mov  (8) msg_reg0.0<1>:UD       tmp_reg0.0<8,8,1>:UD {align1};        
+// send (16) 0 INEP_ROW null read(BIND_IDX_INEP, 0, 0, 4) mlen 1 rlen 1 {align1};
 
 /* COL */
-mul  (2) tmp_reg0.0<1>:D        orig_xy_ub<2,2,1>:UB 16:UW {align1};    /* (x, y) * 16 */
-add  (1) tmp_reg0.0<1>:D        tmp_reg0.0<0,1,0>:D -4:W {align1};     /* X offset */
-mov  (1) tmp_reg0.8<1>:UD       BLOCK_4X16 {align1};
-mov  (1) tmp_reg0.20<1>:UB      thread_id_ub {align1};                  /* dispatch id */
-mov  (8) msg_reg0.0<1>:UD       tmp_reg0.0<8,8,1>:UD {align1};                
-send (16) 0 INEP_COL0 null read(BIND_IDX_INEP, 0, 0, 4) mlen 1 rlen 2 {align1};
+// mul  (2) tmp_reg0.0<1>:D        orig_xy_ub<2,2,1>:UB 16:UW {align1};    /* (x, y) * 16 */
+// add  (1) tmp_reg0.0<1>:D        tmp_reg0.0<0,1,0>:D -4:W {align1};     /* X offset */
+// mov  (1) tmp_reg0.8<1>:UD       BLOCK_4X16 {align1};
+// mov  (1) tmp_reg0.20<1>:UB      thread_id_ub {align1};                  /* dispatch id */
+// mov  (8) msg_reg0.0<1>:UD       tmp_reg0.0<8,8,1>:UD {align1};                
+// send (16) 0 INEP_COL0 null read(BIND_IDX_INEP, 0, 0, 4) mlen 1 rlen 2 {align1};
 
 /*
  * VME message
@@ -172,19 +172,19 @@ mov  (1) tmp_reg1.4<1>:UD       BI_SUB_MB_PART_MASK + MAX_NUM_MV:UD {align1};
 
 mov  (1) intra_part_mask_ub<1>:UB LUMA_INTRA_8x8_DISABLE + LUMA_INTRA_4x4_DISABLE {align1};
 
-cmp.nz.f0.0 (1) null<1>:UW orig_x_ub<0,1,0>:UB 0:UW {align1};                                                   /* X != 0 */
-(f0.0) add (1) mb_intra_struct_ub<1>:UB mb_intra_struct_ub<0,1,0>:UB INTRA_PRED_AVAIL_FLAG_AE {align1};         /* A */
+// cmp.nz.f0.0 (1) null<1>:UW orig_x_ub<0,1,0>:UB 0:UW {align1};                                                   /* X != 0 */
+// (f0.0) add (1) mb_intra_struct_ub<1>:UB mb_intra_struct_ub<0,1,0>:UB INTRA_PRED_AVAIL_FLAG_AE {align1};         /* A */
 
-cmp.nz.f0.0 (1) null<1>:UW orig_y_ub<0,1,0>:UB 0:UW {align1};                                                   /* Y != 0 */
-(f0.0) add (1) mb_intra_struct_ub<1>:UB mb_intra_struct_ub<0,1,0>:UB INTRA_PRED_AVAIL_FLAG_B {align1};          /* B */
+// cmp.nz.f0.0 (1) null<1>:UW orig_y_ub<0,1,0>:UB 0:UW {align1};                                                   /* Y != 0 */
+// (f0.0) add (1) mb_intra_struct_ub<1>:UB mb_intra_struct_ub<0,1,0>:UB INTRA_PRED_AVAIL_FLAG_B {align1};          /* B */
 
-mul.nz.f0.0 (1) null<1>:UW orig_x_ub<0,1,0>:UB orig_y_ub<0,1,0>:UB {align1};                                    /* X * Y != 0 */
-(f0.0) add (1) mb_intra_struct_ub<1>:UB mb_intra_struct_ub<0,1,0>:UB INTRA_PRED_AVAIL_FLAG_D {align1};          /* D */
+// mul.nz.f0.0 (1) null<1>:UW orig_x_ub<0,1,0>:UB orig_y_ub<0,1,0>:UB {align1};                                    /* X * Y != 0 */
+// (f0.0) add (1) mb_intra_struct_ub<1>:UB mb_intra_struct_ub<0,1,0>:UB INTRA_PRED_AVAIL_FLAG_D {align1};          /* D */
 
-add  (1) tmp_x_w<1>:W orig_x_ub<0,1,0>:UB 1:UW {align1};                                                        /* X + 1 */
-add  (1) tmp_x_w<1>:W w_in_mb_uw<0,1,0>:UW -tmp_x_w<0,1,0>:W {align1};                                          /* width - (X + 1) */
-mul.nz.f0.0 (1) null<1>:UD tmp_x_w<0,1,0>:W orig_y_ub<0,1,0>:UB {align1};                                       /* (width - (X + 1)) * Y != 0 */
-(f0.0) add (1) mb_intra_struct_ub<1>:UB mb_intra_struct_ub<0,1,0>:UB INTRA_PRED_AVAIL_FLAG_C {align1};          /* C */
+// add  (1) tmp_x_w<1>:W orig_x_ub<0,1,0>:UB 1:UW {align1};                                                        /* X + 1 */
+// add  (1) tmp_x_w<1>:W w_in_mb_uw<0,1,0>:UW -tmp_x_w<0,1,0>:W {align1};                                          /* width - (X + 1) */
+// mul.nz.f0.0 (1) null<1>:UD tmp_x_w<0,1,0>:W orig_y_ub<0,1,0>:UB {align1};                                       /* (width - (X + 1)) * Y != 0 */
+// (f0.0) add (1) mb_intra_struct_ub<1>:UB mb_intra_struct_ub<0,1,0>:UB INTRA_PRED_AVAIL_FLAG_C {align1};          /* C */
 
 mov  (8) msg_reg1<1>:UD         tmp_reg1.0<8,8,1>:UD {align1};
         
diff --git a/i965_drv_video/shaders/vme/inter_frame.g6b b/i965_drv_video/shaders/vme/inter_frame.g6b
index d497148..cc67117 100644
--- a/i965_drv_video/shaders/vme/inter_frame.g6b
+++ b/i965_drv_video/shaders/vme/inter_frame.g6b
@@ -1,18 +1,5 @@
    { 0x00800001, 0x24000061, 0x00000000, 0x00000000 },
    { 0x00800001, 0x24400061, 0x00000000, 0x00000000 },
-   { 0x00200041, 0x24002e25, 0x004500a0, 0x00100010 },
-   { 0x00000040, 0x24003ca5, 0x00000400, 0xfff8fff8 },
-   { 0x00000040, 0x24043ca5, 0x00000404, 0xffffffff },
-   { 0x00000001, 0x240800e1, 0x00000000, 0x0000001f },
-   { 0x00000001, 0x24140231, 0x00000014, 0x00000000 },
-   { 0x00600001, 0x20000022, 0x008d0400, 0x00000000 },
-   { 0x05800031, 0x22401cdd, 0x00000000, 0x02188004 },
-   { 0x00200041, 0x24002e25, 0x004500a0, 0x00100010 },
-   { 0x00000040, 0x24003ca5, 0x00000400, 0xfffcfffc },
-   { 0x00000001, 0x240800e1, 0x00000000, 0x000f0003 },
-   { 0x00000001, 0x24140231, 0x00000014, 0x00000000 },
-   { 0x00600001, 0x20000022, 0x008d0400, 0x00000000 },
-   { 0x05800031, 0x22801cdd, 0x00000000, 0x02288004 },
    { 0x00200041, 0x24002e29, 0x004500a0, 0x00100010 },
    { 0x00000001, 0x24080021, 0x00000400, 0x00000000 },
    { 0x00000001, 0x240c0061, 0x00000000, 0x00a03000 },
@@ -21,16 +8,6 @@
    { 0x00600001, 0x20000022, 0x008d0400, 0x00000000 },
    { 0x00000001, 0x24240061, 0x00000000, 0x0c000020 },
    { 0x00000001, 0x243c00f1, 0x00000000, 0x00000006 },
-   { 0x02000010, 0x20002e28, 0x000000a0, 0x00000000 },
-   { 0x00010040, 0x243d1e31, 0x0000043d, 0x00000060 },
-   { 0x02000010, 0x20002e28, 0x000000a1, 0x00000000 },
-   { 0x00010040, 0x243d1e31, 0x0000043d, 0x00000010 },
-   { 0x02000041, 0x20004628, 0x000000a0, 0x000000a1 },
-   { 0x00010040, 0x243d1e31, 0x0000043d, 0x00000004 },
-   { 0x00000040, 0x24402e2d, 0x000000a0, 0x00010001 },
-   { 0x00000040, 0x2440352d, 0x000000a2, 0x00004440 },
-   { 0x02000041, 0x200045a0, 0x00000440, 0x000000a1 },
-   { 0x00010040, 0x243d1e31, 0x0000043d, 0x00000008 },
    { 0x00600001, 0x20200022, 0x008d0420, 0x00000000 },
    { 0x00600001, 0x20400022, 0x008d0240, 0x00000000 },
    { 0x00600001, 0x206000e2, 0x00000000, 0x00000000 },