diff options
Diffstat (limited to 'i965_drv_video/shaders/mpeg2/vld/read_field_x1y1_uv.g4i')
-rw-r--r-- | i965_drv_video/shaders/mpeg2/vld/read_field_x1y1_uv.g4i | 53 |
1 files changed, 53 insertions, 0 deletions
diff --git a/i965_drv_video/shaders/mpeg2/vld/read_field_x1y1_uv.g4i b/i965_drv_video/shaders/mpeg2/vld/read_field_x1y1_uv.g4i new file mode 100644 index 0000000..816dd72 --- /dev/null +++ b/i965_drv_video/shaders/mpeg2/vld/read_field_x1y1_uv.g4i @@ -0,0 +1,53 @@ +/* GRF allocation: + g1~g30: constant buffer + g1~g2:intra IQ matrix + g3~g4:non intra IQ matrix + g5~g20:IDCT table + g31: thread payload + g58~g81:reference data + g82: thread payload backup + g83~g106:IDCT data + g115: message descriptor for reading reference data */ +mov (1) g115.8<1>UD 0x07000FUD {align1}; +send (16) 0 g40.0<1>UW g115<8,8,1>UW read(surface_u, 2, 0, 2) mlen 1 rlen 4 {align1};//U +send (16) 0 g45.0<1>UW g115<8,8,1>UW read(surface_v, 2, 0, 2) mlen 1 rlen 4 {align1};//V +mov (1) g115.8<1>UD 0x01000FUD {align1}; +add (1) g115.4<1>UD g115.4<1,1,1>UD 8UD {align1}; +send (16) 0 g44.0<1>UW g115<8,8,1>UW read(surface_u, 2, 0, 2) mlen 1 rlen 1 {align1};//U +send (16) 0 g49.0<1>UW g115<8,8,1>UW read(surface_v, 2, 0, 2) mlen 1 rlen 1 {align1};//V +//U +add (16) g32.0<1>UW g40.0<16,8,1>UB g41.0<16,8,1>UB {align1}; +add (16) g33.0<1>UW g41.0<16,8,1>UB g42.0<16,8,1>UB {align1}; +add (16) g34.0<1>UW g42.0<16,8,1>UB g43.0<16,8,1>UB {align1}; +add (16) g35.0<1>UW g43.0<16,8,1>UB g44.0<16,8,1>UB {align1}; + +add (16) g32.0<1>UW g32.0<16,8,1>UW g40.1<16,8,1>UB {align1}; +add (16) g33.0<1>UW g33.0<16,8,1>UW g41.1<16,8,1>UB {align1}; +add (16) g34.0<1>UW g34.0<16,8,1>UW g42.1<16,8,1>UB {align1}; +add (16) g35.0<1>UW g35.0<16,8,1>UW g43.1<16,8,1>UB {align1}; + +add (16) g32.0<1>UW g32.0<16,8,1>UW g41.1<16,8,1>UB {align1}; +add (16) g33.0<1>UW g33.0<16,8,1>UW g42.1<16,8,1>UB {align1}; +add (16) g34.0<1>UW g34.0<16,8,1>UW g43.1<16,8,1>UB {align1}; +add (16) g35.0<1>UW g35.0<16,8,1>UW g44.1<16,8,1>UB {align1}; +//V +add (16) g36.0<1>UW g45.0<16,8,1>UB g46.0<16,8,1>UB {align1}; +add (16) g37.0<1>UW g46.0<16,8,1>UB g47.0<16,8,1>UB {align1}; +add (16) g38.0<1>UW g47.0<16,8,1>UB g48.0<16,8,1>UB {align1}; +add (16) g39.0<1>UW g48.0<16,8,1>UB g49.0<16,8,1>UB {align1}; + +add (16) g36.0<1>UW g36.0<16,8,1>UW g45.1<16,8,1>UB {align1}; +add (16) g37.0<1>UW g37.0<16,8,1>UW g46.1<16,8,1>UB {align1}; +add (16) g38.0<1>UW g38.0<16,8,1>UW g47.1<16,8,1>UB {align1}; +add (16) g39.0<1>UW g39.0<16,8,1>UW g48.1<16,8,1>UB {align1}; + +add (16) g36.0<1>UW g36.0<16,8,1>UW g46.1<16,8,1>UB {align1}; +add (16) g37.0<1>UW g37.0<16,8,1>UW g47.1<16,8,1>UB {align1}; +add (16) g38.0<1>UW g38.0<16,8,1>UW g48.1<16,8,1>UB {align1}; +add (16) g39.0<1>UW g39.0<16,8,1>UW g49.1<16,8,1>UB {align1}; + +shr (32) g32.0<1>UW g32.0<16,16,1>UW 2UW {align1 compr}; +shr (32) g34.0<1>UW g34.0<16,16,1>UW 2UW {align1 compr}; +shr (32) g36.0<1>UW g36.0<16,16,1>UW 2UW {align1 compr}; +shr (32) g38.0<1>UW g38.0<16,16,1>UW 2UW {align1 compr}; + |