From 9665ba7101509bac76432f2f37921d13ef2ebcca Mon Sep 17 00:00:00 2001 From: "Xiang, Haihao" Date: Tue, 9 Nov 2010 13:07:50 +0800 Subject: i965_drv_video/render: new fragmensts for Sandybridge Signed-off-by: Xiang, Haihao --- configure.ac | 2 +- i965_drv_video/shaders/render/Makefile.am | 23 ++++- .../shaders/render/exa_wm_src_affine.g6a | 47 +++++++++++ .../shaders/render/exa_wm_src_affine.g6b | 4 + .../shaders/render/exa_wm_src_sample_argb.g6a | 48 +++++++++++ .../shaders/render/exa_wm_src_sample_argb.g6b | 3 + .../shaders/render/exa_wm_src_sample_planar.g6a | 58 +++++++++++++ .../shaders/render/exa_wm_src_sample_planar.g6b | 6 ++ i965_drv_video/shaders/render/exa_wm_write.g6a | 77 +++++++++++++++++ i965_drv_video/shaders/render/exa_wm_write.g6b | 17 ++++ i965_drv_video/shaders/render/exa_wm_yuv_rgb.g6a | 98 ++++++++++++++++++++++ i965_drv_video/shaders/render/exa_wm_yuv_rgb.g6b | 11 +++ 12 files changed, 391 insertions(+), 3 deletions(-) create mode 100644 i965_drv_video/shaders/render/exa_wm_src_affine.g6a create mode 100644 i965_drv_video/shaders/render/exa_wm_src_affine.g6b create mode 100644 i965_drv_video/shaders/render/exa_wm_src_sample_argb.g6a create mode 100644 i965_drv_video/shaders/render/exa_wm_src_sample_argb.g6b create mode 100644 i965_drv_video/shaders/render/exa_wm_src_sample_planar.g6a create mode 100644 i965_drv_video/shaders/render/exa_wm_src_sample_planar.g6b create mode 100644 i965_drv_video/shaders/render/exa_wm_write.g6a create mode 100644 i965_drv_video/shaders/render/exa_wm_write.g6b create mode 100644 i965_drv_video/shaders/render/exa_wm_yuv_rgb.g6a create mode 100644 i965_drv_video/shaders/render/exa_wm_yuv_rgb.g6b diff --git a/configure.ac b/configure.ac index 6debe95..aa60df2 100644 --- a/configure.ac +++ b/configure.ac @@ -100,7 +100,7 @@ PKG_CHECK_MODULES([XEXT],[xext]) PKG_CHECK_MODULES([XFIXES], [xfixes]) PKG_CHECK_MODULES([DRM], [libdrm]) -PKG_CHECK_MODULES(GEN4ASM, [intel-gen4asm >= 1.0], [gen4asm=yes], [gen4asm=no]) +PKG_CHECK_MODULES(GEN4ASM, [intel-gen4asm >= 1.1], [gen4asm=yes], [gen4asm=no]) AM_CONDITIONAL(HAVE_GEN4ASM, test x$gen4asm = xyes) # Check for libdrm >= 2.4.21 (needed for i965_drv_video.so) diff --git a/i965_drv_video/shaders/render/Makefile.am b/i965_drv_video/shaders/render/Makefile.am index fb9b11e..ba019af 100644 --- a/i965_drv_video/shaders/render/Makefile.am +++ b/i965_drv_video/shaders/render/Makefile.am @@ -35,17 +35,36 @@ EXTRA_DIST = $(INTEL_G4I) \ $(INTEL_G4B) \ $(INTEL_G4B_GEN5) +INTEL_G6A = \ + exa_wm_src_affine.g6a \ + exa_wm_src_sample_argb.g6a \ + exa_wm_src_sample_planar.g6a \ + exa_wm_write.g6a \ + exa_wm_yuv_rgb.g6a + +INTEL_G6B = \ + exa_wm_src_affine.g6b \ + exa_wm_src_sample_argb.g6b \ + exa_wm_src_sample_planar.g6b \ + exa_wm_write.g6b \ + exa_wm_yuv_rgb.g6b + if HAVE_GEN4ASM -SUFFIXES = .g4a .g4b +SUFFIXES = .g4a .g4b .g6a .g6b .g4a.g4b: m4 $*.g4a > $*.g4m && intel-gen4asm -o $@ $*.g4m && intel-gen4asm -g 5 -o $@.gen5 $*.g4m && rm $*.g4m +.g6a.g6b: + m4 -I$(srcdir) -s $< > $*.g6m && intel-gen4asm -g 6 -o $@ $*.g6m && rm $*.g6m + $(INTEL_G4B): $(INTEL_G4I) +$(INTEL_G6B): $(INTEL_G4I) -BUILT_SOURCES= $(INTEL_G4B) +BUILT_SOURCES= $(INTEL_G4B) $(INTEL_G6B) clean-local: -rm -f $(INTEL_G4B) -rm -f $(INTEL_G4B_GEN5) + -rm -f $(INTEL_G6B) endif diff --git a/i965_drv_video/shaders/render/exa_wm_src_affine.g6a b/i965_drv_video/shaders/render/exa_wm_src_affine.g6a new file mode 100644 index 0000000..08195a4 --- /dev/null +++ b/i965_drv_video/shaders/render/exa_wm_src_affine.g6a @@ -0,0 +1,47 @@ +/* + * Copyright © 2010 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + */ + +/* + * Fragment to compute src u/v values + */ +include(`exa_wm.g4i') + +define(`ul', `src_u') +define(`uh', `m3') +define(`vl', `src_v') +define(`vh', `m5') + +define(`bl', `g2.0<8,8,1>F') +define(`bh', `g4.0<8,8,1>F') + +define(`a0_a_x',`g6.0<0,1,0>F') +define(`a0_a_y',`g6.16<0,1,0>F') + +/* U */ +pln (8) ul<1>F a0_a_x bl { align1 }; /* pixel 0-7 */ +pln (8) uh<1>F a0_a_x bh { align1 }; /* pixel 8-15 */ + +/* V */ +pln (8) vl<1>F a0_a_y bl { align1 }; /* pixel 0-7 */ +pln (8) vh<1>F a0_a_y bh { align1 }; /* pixel 8-15 */ diff --git a/i965_drv_video/shaders/render/exa_wm_src_affine.g6b b/i965_drv_video/shaders/render/exa_wm_src_affine.g6b new file mode 100644 index 0000000..7035e6a --- /dev/null +++ b/i965_drv_video/shaders/render/exa_wm_src_affine.g6b @@ -0,0 +1,4 @@ + { 0x0060005a, 0x204077be, 0x000000c0, 0x008d0040 }, + { 0x0060005a, 0x206077be, 0x000000c0, 0x008d0080 }, + { 0x0060005a, 0x208077be, 0x000000d0, 0x008d0040 }, + { 0x0060005a, 0x20a077be, 0x000000d0, 0x008d0080 }, diff --git a/i965_drv_video/shaders/render/exa_wm_src_sample_argb.g6a b/i965_drv_video/shaders/render/exa_wm_src_sample_argb.g6a new file mode 100644 index 0000000..67bb888 --- /dev/null +++ b/i965_drv_video/shaders/render/exa_wm_src_sample_argb.g6a @@ -0,0 +1,48 @@ +/* + * Copyright © 2006 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Authors: + * Wang Zhenyu + * Keith Packard + */ + +/* Sample the src surface */ + +include(`exa_wm.g4i') + +/* prepare sampler read back gX register, which would be written back to output */ + +/* use simd16 sampler, param 0 is u, param 1 is v. */ +/* 'payload' loading, assuming tex coord start from g4 */ + +/* load argb */ +mov (1) g0.8<1>UD 0x00000000UD { align1 mask_disable }; +mov (8) src_msg<1>UD g0<8,8,1>UD { align1 mask_disable }; + +/* src_msg will be copied with g0, as it contains send desc */ +/* emit sampler 'send' cmd */ +send (16) src_msg_ind /* msg reg index */ + src_sample_base<1>UW /* readback */ + null + sampler (1,0,F) /* sampler message description, (binding_table,sampler_index,datatype) + /* here(src->dst) we should use src_sampler and src_surface */ + mlen 5 rlen 8 { align1 }; /* required message len 5, readback len 8 */ diff --git a/i965_drv_video/shaders/render/exa_wm_src_sample_argb.g6b b/i965_drv_video/shaders/render/exa_wm_src_sample_argb.g6b new file mode 100644 index 0000000..2846491 --- /dev/null +++ b/i965_drv_video/shaders/render/exa_wm_src_sample_argb.g6b @@ -0,0 +1,3 @@ + { 0x00000201, 0x20080061, 0x00000000, 0x00000000 }, + { 0x00600201, 0x20200022, 0x008d0000, 0x00000000 }, + { 0x02800031, 0x21c01cc9, 0x00000020, 0x0a8a0001 }, diff --git a/i965_drv_video/shaders/render/exa_wm_src_sample_planar.g6a b/i965_drv_video/shaders/render/exa_wm_src_sample_planar.g6a new file mode 100644 index 0000000..1f78629 --- /dev/null +++ b/i965_drv_video/shaders/render/exa_wm_src_sample_planar.g6a @@ -0,0 +1,58 @@ +/* + * Copyright © 2006 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Authors: + * Wang Zhenyu + * Keith Packard + */ + +/* Sample the src surface in planar format */ + +include(`exa_wm.g4i') + +/* prepare sampler read back gX register, which would be written back to output */ + +/* use simd16 sampler, param 0 is u, param 1 is v. */ +/* 'payload' loading, assuming tex coord start from g4 */ + +mov (1) g0.8<1>UD 0x0000c000UD { align1 mask_disable }; +mov (8) src_msg<1>UD g0<8,8,1>UD { align1 mask_disable }; + +/* sample UV (CrCb) */ +send (16) src_msg_ind /* msg reg index */ + src_sample_g<1>UW /* readback */ + null + sampler (3,2,F) /* sampler message description, (binding_table,sampler_index,datatype) + /* here(src->dst) we should use src_sampler and src_surface */ + mlen 5 rlen 4 { align1 }; /* required message len 5, readback len 8 */ + +mov (1) g0.8<1>UD 0x0000e000UD { align1 mask_disable }; +mov (8) src_msg<1>UD g0<8,8,1>UD { align1 mask_disable }; + +/* sample Y */ +send (16) src_msg_ind /* msg reg index */ + src_sample_r<1>UW /* readback */ + null + sampler (1,0,F) /* sampler message description, (binding_table,sampler_index,datatype) + /* here(src->dst) we should use src_sampler and src_surface */ + mlen 5 rlen 2 { align1 }; /* required message len 5, readback len 8 */ + diff --git a/i965_drv_video/shaders/render/exa_wm_src_sample_planar.g6b b/i965_drv_video/shaders/render/exa_wm_src_sample_planar.g6b new file mode 100644 index 0000000..ef45022 --- /dev/null +++ b/i965_drv_video/shaders/render/exa_wm_src_sample_planar.g6b @@ -0,0 +1,6 @@ + { 0x00000201, 0x20080061, 0x00000000, 0x0000c000 }, + { 0x00600201, 0x20200022, 0x008d0000, 0x00000000 }, + { 0x02800031, 0x22001cc9, 0x00000020, 0x0a4a0203 }, + { 0x00000201, 0x20080061, 0x00000000, 0x0000e000 }, + { 0x00600201, 0x20200022, 0x008d0000, 0x00000000 }, + { 0x02800031, 0x21c01cc9, 0x00000020, 0x0a2a0001 }, diff --git a/i965_drv_video/shaders/render/exa_wm_write.g6a b/i965_drv_video/shaders/render/exa_wm_write.g6a new file mode 100644 index 0000000..c0f3cc1 --- /dev/null +++ b/i965_drv_video/shaders/render/exa_wm_write.g6a @@ -0,0 +1,77 @@ +/* + * Copyright © 2010 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + */ + +include(`exa_wm.g4i') + +/* + * Prepare data in m2-m3 for Red channel, m4-m5 for Green channel, + * m6-m7 for Blue and m8-m9 for Alpha channel + */ +define(`slot_r_00', `m2') +define(`slot_r_01', `m3') +define(`slot_g_00', `m4') +define(`slot_g_01', `m5') +define(`slot_b_00', `m6') +define(`slot_b_01', `m7') +define(`slot_a_00', `m8') +define(`slot_a_01', `m9') +define(`data_port_msg_2_ind', `2') + +mov (8) slot_r_00<1>F src_sample_r_01<8,8,1>F { align1 }; +mov (8) slot_r_01<1>F src_sample_r_23<8,8,1>F { align1 }; + +mov (8) slot_g_00<1>F src_sample_g_01<8,8,1>F { align1 }; +mov (8) slot_g_01<1>F src_sample_g_23<8,8,1>F { align1 }; + +mov (8) slot_b_00<1>F src_sample_b_01<8,8,1>F { align1 }; +mov (8) slot_b_01<1>F src_sample_b_23<8,8,1>F { align1 }; + +mov (8) slot_a_00<1>F src_sample_a_01<8,8,1>F { align1 }; +mov (8) slot_a_01<1>F src_sample_a_23<8,8,1>F { align1 }; + +/* write */ +send (16) + data_port_msg_2_ind + acc0<1>UW + null + write ( + 0, /* binding_table */ + 16, /* pixel scordboard clear, msg type simd16 single source */ + 12, /* render target write */ + 0, /* no write commit message */ + 0 /* headerless render target write */ + ) + mlen 8 + rlen 0 + { align1 EOT }; + +nop; +nop; +nop; +nop; +nop; +nop; +nop; +nop; + diff --git a/i965_drv_video/shaders/render/exa_wm_write.g6b b/i965_drv_video/shaders/render/exa_wm_write.g6b new file mode 100644 index 0000000..3cb6bff --- /dev/null +++ b/i965_drv_video/shaders/render/exa_wm_write.g6b @@ -0,0 +1,17 @@ + { 0x00600001, 0x204003be, 0x008d01c0, 0x00000000 }, + { 0x00600001, 0x206003be, 0x008d01e0, 0x00000000 }, + { 0x00600001, 0x208003be, 0x008d0200, 0x00000000 }, + { 0x00600001, 0x20a003be, 0x008d0220, 0x00000000 }, + { 0x00600001, 0x20c003be, 0x008d0240, 0x00000000 }, + { 0x00600001, 0x20e003be, 0x008d0260, 0x00000000 }, + { 0x00600001, 0x210003be, 0x008d0280, 0x00000000 }, + { 0x00600001, 0x212003be, 0x008d02a0, 0x00000000 }, + { 0x05800031, 0x24001cc8, 0x00000040, 0x90019000 }, + { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, + { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, + { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, + { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, + { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, + { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, + { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, + { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, diff --git a/i965_drv_video/shaders/render/exa_wm_yuv_rgb.g6a b/i965_drv_video/shaders/render/exa_wm_yuv_rgb.g6a new file mode 100644 index 0000000..5b9e625 --- /dev/null +++ b/i965_drv_video/shaders/render/exa_wm_yuv_rgb.g6a @@ -0,0 +1,98 @@ +/* + * Copyright © 2006 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Authors: + * Keith Packard + * Eric Anholt + * + */ + +include(`exa_wm.g4i') + +define(`YCbCr_base', `src_sample_base') + +define(`Cr', `src_sample_b') +define(`Cr_01', `src_sample_b_01') +define(`Cr_23', `src_sample_b_23') + +define(`Y', `src_sample_r') +define(`Y_01', `src_sample_r_01') +define(`Y_23', `src_sample_r_23') + +define(`Cb', `src_sample_g') +define(`Cb_01', `src_sample_g_01') +define(`Cb_23', `src_sample_g_23') + +define(`Crn', `mask_sample_g') +define(`Crn_01', `mask_sample_g_01') +define(`Crn_23', `mask_sample_g_23') + +define(`Yn', `mask_sample_r') +define(`Yn_01', `mask_sample_r_01') +define(`Yn_23', `mask_sample_r_23') + +define(`Cbn', `mask_sample_b') +define(`Cbn_01', `mask_sample_b_01') +define(`Cbn_23', `mask_sample_b_23') + + /* color space conversion function: + * R = Clamp ( 1.164(Y-16/255) + 1.596(Cr-128/255), 0, 1) + * G = Clamp ( 1.164(Y-16/255) - 0.813(Cr-128/255) - 0.392(Cb-128/255), 0, 1) + * B = Clamp ( 1.164(Y-16/255) + 2.017(Cb-128/255), 0, 1) + */ + + /* Normalize Y, Cb and Cr: + * + * Yn = (Y - 16/255) * 1.164 + * Crn = Cr - 128 / 255 + * Cbn = Cb - 128 / 255 + */ +add (16) Yn<1>F Y<8,8,1>F -0.0627451F { compr align1 }; +mul (16) Yn<1>F Yn<8,8,1>F 1.164F { compr align1 }; + +add (16) Crn<1>F Cr<8,8,1>F -0.501961F { compr align1 }; + +add (16) Cbn<1>F Cb<8,8,1>F -0.501961F { compr align1 }; + + /* + * R = Y + Cr * 1.596 + */ +mov (16) acc0<1>F Yn<8,8,1>F { compr align1 }; +mac.sat(16) src_sample_r<1>F Crn<8,8,1>F 1.596F { compr align1 }; + + /* + * G = Crn * -0.813 + Cbn * -0.392 + Y + */ +mov (16) acc0<1>F Yn<8,8,1>F { compr align1 }; +mac (16) acc0<1>F Crn<8,8,1>F -0.813F { compr align1 }; +mac.sat(16) src_sample_g<1>F Cbn<8,8,1>F -0.392F { compr align1 }; + + /* + * B = Cbn * 2.017 + Y + */ +mov (16) acc0<1>F Yn<8,8,1>F { compr align1 }; +mac.sat(16) src_sample_b<1>F Cbn<8,8,1>F 2.017F { compr align1 }; + + /* + * A = 1.0 + */ +//mov (16) src_sample_a<1>F 1.0F { compr align1 }; diff --git a/i965_drv_video/shaders/render/exa_wm_yuv_rgb.g6b b/i965_drv_video/shaders/render/exa_wm_yuv_rgb.g6b new file mode 100644 index 0000000..21fa6fb --- /dev/null +++ b/i965_drv_video/shaders/render/exa_wm_yuv_rgb.g6b @@ -0,0 +1,11 @@ + { 0x00800040, 0x22c07fbd, 0x008d01c0, 0xbd808081 }, + { 0x00800041, 0x22c07fbd, 0x008d02c0, 0x3f94fdf4 }, + { 0x00800040, 0x23007fbd, 0x008d0240, 0xbf008084 }, + { 0x00800040, 0x23407fbd, 0x008d0200, 0xbf008084 }, + { 0x00800001, 0x240003bc, 0x008d02c0, 0x00000000 }, + { 0x80800048, 0x21c07fbd, 0x008d0300, 0x3fcc49ba }, + { 0x00800001, 0x240003bc, 0x008d02c0, 0x00000000 }, + { 0x00800048, 0x24007fbc, 0x008d0300, 0xbf5020c5 }, + { 0x80800048, 0x22007fbd, 0x008d0340, 0xbec8b439 }, + { 0x00800001, 0x240003bc, 0x008d02c0, 0x00000000 }, + { 0x80800048, 0x22407fbd, 0x008d0340, 0x40011687 }, -- cgit v1.2.1