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| author | Thierry Reding <treding@nvidia.com> | 2015-12-30 17:13:29 +0100 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2016-02-15 19:54:14 +0100 |
| commit | 0104c480bce36b17b56d0f22ca635519a69f39e8 (patch) | |
| tree | 71d7f142ffebe9f2d9e8de679e45f2ca450c7cf1 | |
| parent | 55c3a1ec3a2fc76f36b82d3ea34b9f2104567c8b (diff) | |
| download | linux-next-0104c480bce36b17b56d0f22ca635519a69f39e8.tar.gz | |
soc/tegra: pmc: Use register definitions instead of magic values
Use register definitions for the main SoC reset operation instead of
hard-coding magic values. Note that the PMC_RST_STATUS register isn't
actually accessed, but since it is mentioned in a comment the
definitions are added for completeness.
Signed-off-by: Thierry Reding <treding@nvidia.com>
| -rw-r--r-- | drivers/soc/tegra/pmc.c | 16 |
1 files changed, 13 insertions, 3 deletions
diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index 2651eb586fb3..72d337c5c67f 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -47,6 +47,7 @@ #define PMC_CNTRL_CPU_PWRREQ_POLARITY (1 << 15) /* CPU pwr req polarity */ #define PMC_CNTRL_CPU_PWRREQ_OE (1 << 16) /* CPU pwr req enable */ #define PMC_CNTRL_INTR_POLARITY (1 << 17) /* inverts INTR polarity */ +#define PMC_CNTRL_MAIN_RST (1 << 4) #define DPD_SAMPLE 0x020 #define DPD_SAMPLE_ENABLE (1 << 0) @@ -76,6 +77,14 @@ #define PMC_SENSOR_CTRL_SCRATCH_WRITE (1 << 2) #define PMC_SENSOR_CTRL_ENABLE_RST (1 << 1) +#define PMC_RST_STATUS 0x1b4 +#define PMC_RST_STATUS_AOTAG (1 << 5) +#define PMC_RST_STATUS_LP0 (1 << 4) +#define PMC_RST_STATUS_SW_MAIN (1 << 3) +#define PMC_RST_STATUS_SENSOR (1 << 2) +#define PMC_RST_STATUS_WATCHDOG (1 << 1) +#define PMC_RST_STATUS_POR (1 << 0) + #define IO_DPD_REQ 0x1b8 #define IO_DPD_REQ_CODE_IDLE (0 << 30) #define IO_DPD_REQ_CODE_OFF (1 << 30) @@ -405,9 +414,10 @@ static int tegra_pmc_restart_notify(struct notifier_block *this, tegra_pmc_writel(value, PMC_SCRATCH0); - value = tegra_pmc_readl(0); - value |= 0x10; - tegra_pmc_writel(value, 0); + /* reset everything but PMC_SCRATCH0 and PMC_RST_STATUS */ + value = tegra_pmc_readl(PMC_CNTRL); + value |= PMC_CNTRL_MAIN_RST; + tegra_pmc_writel(value, PMC_CNTRL); return NOTIFY_DONE; } |