diff options
| author | Vince Hsu <vince.h@nvidia.com> | 2015-07-13 19:08:05 +0800 |
|---|---|---|
| committer | Alexandre Courbot <acourbot@nvidia.com> | 2016-03-11 12:29:39 +0900 |
| commit | e5e0955cb847d80f8b0cec5bc952cae7f3f9053d (patch) | |
| tree | ed8b27f4ceb4c0627a416266972c818f6961d31d | |
| parent | 614ec175369b639001b2957672efe9a4204658b5 (diff) | |
| download | linux-next-e5e0955cb847d80f8b0cec5bc952cae7f3f9053d.tar.gz | |
CHROMIUM: clk: tegra: set proper flags for gpu and pllg_ref clocks
The reset of gpu and pllg_ref clocks is controlled by the GPU driver.
Set the proper flags to bypass reset in clock framework
BUG=chrome-os-partner:40712
TEST=Can boot to UI
Change-Id: Ieac9ce397ed93b6d3d16e602c6b912088800aaef
Signed-off-by: Vince Hsu <vince.h@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/285034
Reviewed-by: Tomasz Figa <tfiga@chromium.org>
| -rw-r--r-- | drivers/clk/tegra/clk-tegra-periph.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/clk/tegra/clk-tegra-periph.c b/drivers/clk/tegra/clk-tegra-periph.c index f9c5c0be50a2..96a9a29ebb10 100644 --- a/drivers/clk/tegra/clk-tegra-periph.c +++ b/drivers/clk/tegra/clk-tegra-periph.c @@ -1009,8 +1009,8 @@ static struct tegra_periph_init_data gate_clks[] = { GATE("ispb", "clk_m", 3, 0, tegra_clk_ispb, 0), GATE("vim2_clk", "clk_m", 11, 0, tegra_clk_vim2_clk, 0), GATE("pcie", "clk_m", 70, 0, tegra_clk_pcie, 0), - GATE("gpu", "pll_ref", 184, 0, tegra_clk_gpu, 0), - GATE("pllg_ref", "pll_ref", 189, 0, tegra_clk_pll_g_ref, 0), + GATE("gpu", "pll_ref", 184, TEGRA_PERIPH_MANUAL_RESET, tegra_clk_gpu, 0), + GATE("pllg_ref", "pll_ref", 189, TEGRA_PERIPH_NO_RESET, tegra_clk_pll_g_ref, 0), GATE("hsic_trk", "usb2_hsic_trk", 209, TEGRA_PERIPH_NO_RESET, tegra_clk_hsic_trk, 0), GATE("usb2_trk", "usb2_hsic_trk", 210, TEGRA_PERIPH_NO_RESET, tegra_clk_usb2_trk, 0), GATE("xusb_gate", "osc", 143, 0, tegra_clk_xusb_gate, 0), |