diff options
| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2016-05-20 09:09:53 +0200 |
|---|---|---|
| committer | Simon Horman <horms+renesas@verge.net.au> | 2016-05-30 09:37:09 +0900 |
| commit | b0da45c60d2f7b08128a6cd1216ac0ac7d8954c7 (patch) | |
| tree | 5c271008346f0da88fcbcdda360e4804a80b746f /arch/arm/boot/dts/r8a73a4.dtsi | |
| parent | 33df2753637b2d59adcfd13c35761ff13ff1c673 (diff) | |
| download | linux-next-b0da45c60d2f7b08128a6cd1216ac0ac7d8954c7.tar.gz | |
ARM: dts: r8a73a4: Fix W=1 dtc warnings
Warning (unit_address_vs_reg): Node /cache-controller@0 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /cache-controller@1 has a unit name, but no reg property
Move the cache-controller nodes under the cpus node, and make their
unit names and reg properties match the MPIDR values.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm/boot/dts/r8a73a4.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/r8a73a4.dtsi | 34 |
1 files changed, 18 insertions, 16 deletions
diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi index 6954912a3753..ca8672778fe0 100644 --- a/arch/arm/boot/dts/r8a73a4.dtsi +++ b/arch/arm/boot/dts/r8a73a4.dtsi @@ -31,6 +31,24 @@ power-domains = <&pd_a2sl>; next-level-cache = <&L2_CA15>; }; + + L2_CA15: cache-controller@0 { + compatible = "cache"; + reg = <0>; + clocks = <&cpg_clocks R8A73A4_CLK_Z>; + power-domains = <&pd_a3sm>; + cache-unified; + cache-level = <2>; + }; + + L2_CA7: cache-controller@100 { + compatible = "cache"; + reg = <0x100>; + clocks = <&cpg_clocks R8A73A4_CLK_Z2>; + power-domains = <&pd_a3km>; + cache-unified; + cache-level = <2>; + }; }; ptm { @@ -46,22 +64,6 @@ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; }; - L2_CA15: cache-controller@0 { - compatible = "cache"; - clocks = <&cpg_clocks R8A73A4_CLK_Z>; - power-domains = <&pd_a3sm>; - cache-unified; - cache-level = <2>; - }; - - L2_CA7: cache-controller@1 { - compatible = "cache"; - clocks = <&cpg_clocks R8A73A4_CLK_Z2>; - power-domains = <&pd_a3km>; - cache-unified; - cache-level = <2>; - }; - dbsc1: memory-controller@e6790000 { compatible = "renesas,dbsc-r8a73a4"; reg = <0 0xe6790000 0 0x10000>; |