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| author | Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> | 2020-05-27 22:18:40 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2020-06-15 10:28:46 +0200 |
| commit | 5818cc37e7fc72d9f2da255d9648c5f2e1a33b22 (patch) | |
| tree | cc220f4c6aa1c40d39c69b26f87aa90916be61b3 /arch/arm/boot/dts | |
| parent | 937c9ebddc09284dc947afaae52c76d05ee1dcfd (diff) | |
| download | linux-next-5818cc37e7fc72d9f2da255d9648c5f2e1a33b22.tar.gz | |
ARM: dts: r8a7742: Add CMT SoC specific support
Add CMT[01] support to r8a7742 SoC DT.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Link: https://lore.kernel.org/r/1590614320-30160-5-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'arch/arm/boot/dts')
| -rw-r--r-- | arch/arm/boot/dts/r8a7742.dtsi | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/r8a7742.dtsi b/arch/arm/boot/dts/r8a7742.dtsi index f57db0572b64..08af9e2943cb 100644 --- a/arch/arm/boot/dts/r8a7742.dtsi +++ b/arch/arm/boot/dts/r8a7742.dtsi @@ -1368,6 +1368,38 @@ compatible = "renesas,prr"; reg = <0 0xff000044 0 4>; }; + + cmt0: timer@ffca0000 { + compatible = "renesas,r8a7742-cmt0", + "renesas,rcar-gen2-cmt0"; + reg = <0 0xffca0000 0 0x1004>; + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 124>; + clock-names = "fck"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 124>; + status = "disabled"; + }; + + cmt1: timer@e6130000 { + compatible = "renesas,r8a7742-cmt1", + "renesas,rcar-gen2-cmt1"; + reg = <0 0xe6130000 0 0x1004>; + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 329>; + clock-names = "fck"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 329>; + status = "disabled"; + }; }; thermal-zones { |